Area Optimization Techniques for High-Density Spin-Orbit Torque MRAMs

Abstract

This paper presents area optimization techniques for high-density spin-orbit torque magnetic random-access memories (SOT-MRAMs). Although SOT-MRAM has many desirable features of nonvolatility, high reliability and low write energy, it poses challenges to high-density memory implementation because of the use of two access transistors per cell. We first analyze the layout of the conventional SOT-MRAM bit-cell that includes two vertical metal lines, a bit-line and a source-line, limiting the horizontal dimension. We further propose two design techniques to reduce the horizontal dimension by decreasing the number of metal lines per cell without any performance overhead. Based on the fact that adjacent columns in a bit-interleaved array are not simultaneously accessed, the proposed techniques share a single source-line between two consecutive bit-cells in the same row. The simulation result shows that proposed techniques can achieve a bit-cell area reduction of 10–25% compared to the conventional SOT-MRAM. The comparison of our proposed designs with the standard spin-transfer torque MRAM shows 45% lower write energy, 84% lower read energy, and 2.3 × higher read-disturb margin.

Ultra High-Density SOT-MRAM Design for Last-Level On-Chip Cache Application

“…This biasing condition allows a small current to flow from terminal T 1 to terminal T 3 of the SOT device, facilitating the sensing of stored data by comparing it with the current from a reference cell. Figure 2b displays the separation of the write and read paths, permitting independent optimization of each memory operation without interference [5,15].…”

“…Spin-transfer torque magnetic random-access memory (STT-MRAM) has garnered significant interest as an excellent prospect for on-chip cache memory applications, owing to its advantageous attributes, such as high integration density, low leakage power consumption, inherent nonvolatility, and compatibility with the complementary metaloxide-semiconductor (CMOS) fabrication process [1][2][3][4][5][6][7][8][9][10].…”

“…The research on reducing the horizontal dimension is focused on decreasing the number of metal lines routed in vertical dimensions, such as the bit line (BL) and source line (SL). Sharing source-line SOT-MRAM architecture is also proposed in [5] to improve the horizontal dimension. In [15], the horizontal dimension can be reduced by routing the SL in the horizontal direction.…”

Multi-bit MRAM based high performance neuromorphic accelerator for image classification

“…Spin-based devices can be stacked vertically utilizing the back end of line fabrication technique to implement computation-in-memory (CIM) applications. A multi-level bit-cell (MLC) is a well-known technique for improving the integration density and reducing the cost/bit [6]. Multi-bit device topologies are well suited for compensating area overhead due to additional access CMOS transistors to design and implement an energy-efficient memory and architectures.…”

STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks

“…SOT-MRAM-based works are reported in [11] and [12] perform only bulk bit-wise logic operations among a few operands, prohibiting highlyparallel single-access MAC operations. The PXNOR-BNN architecture in [12] is a write scheme-based solution, its energy per operation is increased by the extensive usage of write accesses, whose energy is well known to be higher than read [19]. However, the low tunneling magnetoresistance ratio (TMR) as known as the major challenge of STT-MRAM that makes it is difficult to apply STT-MRAM for analog This work is licensed under a Creative Commons Attribution 4.0 License.…”