Area Optimized FPGA-Based Implementation of The Sobel Compass Edge Detector

Abstract

This paper presents a new FPGA resource optimized hardware architecture for real-time edge detection using the Sobel compass operator. The architecture uses a single processing element to compute the gradient for all directions. This greatly economizes on the FPGA resources' usages (more than 40% reduction) while maintaining real-time video frame rates. The measured performance of the architecture is 50 fps for standard PAL size video and 200 fps for CIF size video. The use of pipelining further improved the performance (185 fps for PAL size video and 740 fps for CIF size video) without significant increase in FPGA resources.

Comparative analysis of different optimization technique for Sobel edge detection on FPGA

“…b. Area optimized gradient calculation unit [4] c. Proposed gradient calculation unit iii. Binary Segmentation module In this architecture, Data input are the pixel values of the Gray Scale Image, Result is the output of the edge detection operator, and generation data and gradient are the middle signals.…”

“…Each processing element (PE) performs the same set of operations (addition, subtraction and multiplication by 2) on input applied them. Here only difference for four gradient computation units (PE0, PE45, PE90 and PE135) is in inputs applied to them at a particular time [4]. Therefore, by switching the inputs applied to anyone of processing element in appropriate manner, the same processing element can be used to compute all four gradients along different directions.…”

“…Therefore, by switching the inputs applied to anyone of processing element in appropriate manner, the same processing element can be used to compute all four gradients along different directions. The advantage of this architecture is it requires less FPGA resources compared to the standard architecture [4]. But drawback of this architecture is delay is high.…”

“…The drawback of this paper is it requires more FPGA resources. In second paper [4] the author discussed the area optimized Sobel operator, which uses only one processing element to compute the gradient for all the direction. It requires less FPGA resources.…”

“…In this paper we discuss an optimized Sobel operator, it needs less FPGA resources and also reduces delay compared to reference [3] and reference [4].…”