Area reduction techniques for BIST PLA's

Abstract

Programmable Logic Arrays (PLA's) are widely w e d an VLSI system becawe of their compactness, eade in automatic design, and regularity in their structure. This paper describer rome techniques to reduce the chip area of a PLA containing self-testing circuitry. In particular, we introduce some variants to the method presented in [5] which allow w to further minimize the amount of logic required to realize the BIST mechanism. Some ezperimental results on the implementation of a real Self-Testing PLA are given an order to show the effectiveness of our approach.