2017
DOI: 10.1109/tc.2017.2672984
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Area-Time Efficient Computation of Niederreiter Encryption on QC-MDPC Codes for Embedded Hardware

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Cited by 17 publications
(5 citation statements)
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“…When the maximum number of decoding iterations is set to a limited number, such as I max = 30, the FER of the row-layered decoder is also lower due to the faster convergence. Most previous MDPC decoder designs consider BF algorithms [6]- [12] due to their simplicity. For comparison, simulation results of the REMP-2 BF algorithm [6] with optimal parameter settings are included in Fig.…”
Section: Row-layered Scheduling Schemementioning
confidence: 99%
See 1 more Smart Citation
“…When the maximum number of decoding iterations is set to a limited number, such as I max = 30, the FER of the row-layered decoder is also lower due to the faster convergence. Most previous MDPC decoder designs consider BF algorithms [6]- [12] due to their simplicity. For comparison, simulation results of the REMP-2 BF algorithm [6] with optimal parameter settings are included in Fig.…”
Section: Row-layered Scheduling Schemementioning
confidence: 99%
“…A spectrum of algorithms can be used to decode MDPC codes, with the bit-flipping (BF) algorithm and its variations being the simplest and having been explored in quite a few recent works [6]- [9]. The BF MDPC decoder implementations in [10]- [12] divide each column of the parity check matrix into L-bit segments, which are processed one by one to reduce the decoding latency. However, the parity check matrices of MDPC codes are still very sparse.…”
Section: Introductionmentioning
confidence: 99%
“…Considering implementation work, Hu and Cheung presented a hardware implementation of QC‐MDPC codes partially based on QcBits implementation. Using a Xilinx Virtex‐6 FPGA, they achieved a 53% area‐time product gain comparing to the previous designs for QC‐MDPC codes.…”
Section: Related Workmentioning
confidence: 99%
“…No effective countermeasure was proposed for this attack yet. Considering implementation work, Hu and Cheung [Hu and Cheung 2017] presented a hardware implementation of QC-MDPC codes partially based on QcBits implementation. Using a Xilinx Virtex-6 FPGA, they achieved a 53% area-time product gain comparing to the previous designs for QC-MDPC codes.…”
Section: Related Workmentioning
confidence: 99%