Area-Time Efficient Two-Dimensional Reconfigurable Integer DCT Architecture for HEVC

Meher, Pramod Kumar; Lam, Siew-Kei; Srikanthan, Thambipillai; Kim, Dong Hwan; Park, Sang Yoon

doi:10.3390/electronics10050603

Cited by 3 publications

(2 citation statements)

References 12 publications

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“…Maher and Srikanthan demonstrated that parallel topologies for 1D integer DCT of varying lengths can be derived from matrix multiplication schemes utilizing minimal adders. The suggested 2D DCT architecture makes use of a unique transposition buffer that, without altering the dimension of the transposition buffer, gives twice the throughput of existing solutions [25]. However, the N point 1D-DCT architecture involves the N/2 point 1D-DCT blocks.…”

Section: Existing Modelsmentioning

confidence: 99%

An Improved VLSI Architectural Design of Discrete Cosine Transform Based on the Loeffler-DCT Algorithm

2023

IJIES

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The Discrete Cosine Transform (DCT) is a basic transform block used in Adaptive Multicore Transform (AMT), which is a core of High Efficiency Video Coding (HEVC) and Versatile Video Coding (VVC) standards. AMT uses artificial intelligence technique to decide on the transform output. The suggested One-Dimensional DCT architecture is conceived by 8-point structure Loeffler-DCT technique and synthesized using a floating-point Arithmetic. By preserving the structural regularity as the Loeffler-based design, the optimized floating-point architecture consumes optimum space and delay thereby increasing the precision. The work focuses on obtaining high precision output without compromising on ADP (Area-Delay-Product). Due to the fact that the floating-point multiplier unit is developed using shift-add operations, the results reveal the accomplishment of better resolution output while maintaining Root Mean Square deviation as low as 0.0062. A total of 117 additions, 66 shifts are employed in the suggested architecture. The proposed 1D-DCT is used as a sub-block in developing the architecture of 2D-DCT using only 50% of the 1D-DCT subblocks that is needed for the conventional technique. The 8 X 8 2-D DCT, is computed using only 8 1-D DCT's and additions, instead of using 16 1-D DCT's, as in the traditional row-column method. The model is tested with standard images, which resulted in better PSNR and MSE compared to the standard method. In comparison to the state-of-the-art on DCT, the proposed method obtains a root mean square error that is negligible up to three decimal places resulting in improvement of PSNR by 17%, with a maximum clock frequency of 496MHz has been achieved. The proposed design strikes a balance between trade-off parameters such as area, speed, and precision.

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Section: Existing Modelsmentioning

confidence: 99%

An Improved VLSI Architectural Design of Discrete Cosine Transform Based on the Loeffler-DCT Algorithm

2023

IJIES

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“…Several 8-point approximated DCTs are proposed in [16][17][18] with different techniques to derive efficient transforms with a lower number of required additions. Larger transforms such as 16-point DCT can offer better performances as more coding gains compared with 4-point or 8-point transforms [19][20][21].…”

Section: Introductionmentioning

confidence: 99%

An Efficient Algorithm and Architecture for the VLSI Implementation of Integer DCT That Allows an Efficient Incorporation of the Hardware Security with a Low Overhead

Chiper

Cracan

2023

Applied Sciences

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In this paper, we propose a new hardware algorithm for an integer based discrete cosine transform (IntDCT) that was designed to allow an efficient VLSI implementation of the discrete cosine transform using the systolic array architectural paradigm. The proposed algorithm demonstrates multiple benefits specific to integer transforms with efficient hardware implementation and sufficient precision in approximating irrational transform coefficients for practical applications. The proposed integer DCT algorithm can be efficiently restructured into five regular and modular computational structures of lengths of four and one of length two called pseudo-cycle convolutions which translate into efficient VLSI implementations using systolic arrays. Moreover, besides an efficient VLSI implementation with high-speed performances due to the parallel decomposition of the proposed integer DCT algorithm, the proposed VLSI architecture uses a tag control mechanism that facilitates the integration of an obfuscation technique that significantly improves the hardware security with low overheads, maintaining all the implementation performances.

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Multi-transform 2D DCT Architecture Supporting AVC and HEVC Video Codec

Sai

Mamatha

2022

Advances in Data Computing, Communication and Security

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Area-Time Efficient Two-Dimensional Reconfigurable Integer DCT Architecture for HEVC

Cited by 3 publications

References 12 publications

An Improved VLSI Architectural Design of Discrete Cosine Transform Based on the Loeffler-DCT Algorithm

An Improved VLSI Architectural Design of Discrete Cosine Transform Based on the Loeffler-DCT Algorithm

An Efficient Algorithm and Architecture for the VLSI Implementation of Integer DCT That Allows an Efficient Incorporation of the Hardware Security with a Low Overhead

Multi-transform 2D DCT Architecture Supporting AVC and HEVC Video Codec

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