ARENA: Asynchronous Reconfigurable Accelerator Ring to Enable Data-Centric Parallel Computing

Abstract

The next generation HPC and data centers are likely to be reconfigurable and data-centric due to the trend of hardware specialization and the emergence of data-driven applications. In this paper, we propose ARENA -an asynchronous reconfigurable accelerator ring architecture as a potential scenario on how the future HPC and data centers will be like. Despite using the coarse-grained reconfigurable arrays (CGRAs) as the substrate platform, our key contribution is not only the CGRA-cluster design itself, but also the ensemble of a new architecture and programming model that enables asynchronous tasking across a cluster of reconfigurable nodes, so as to bring specialized computation to the data rather than the reverse. We presume distributed data storage without asserting any prior knowledge on the data distribution. Hardware specialization occurs at runtime when a task finds the majority of data it requires are available at the present node. In other words, we dynamically generate specialized CGRA accelerators where the data reside. The asynchronous tasking for bringing computation to data is achieved by circulating the task token, which describes the dataflow graphs to be executed for a task, among the CGRA cluster connected by a fast ring network. Evaluations on a set of HPC and data-driven applications across different domains show that ARENA can provide better parallel scalability with reduced data movement (53.9%). Compared with contemporary compute-centric parallel models, ARENA can bring on average 4.37× speedup. The synthesized CGRAs and their task-dispatchers only occupy 2.93mm 2 chip area under 45nm process technology and can run at 800MHz with on average 759.8mW power consumption. ARENA also supports the concurrent execution of multi-applications, offering ideal architectural support for future high-performance parallel computing and data analytics systems.

Automatic Compilation of CNN on Reconfigurable Array Processor Based on Scalable Instruction Group Library

“…W ITH the flourishing development of CNN, more and more application fields have benefited from its advancement. However, the typical high-density characteristics of CNN, including intensive computation and memory access, impose higher requirements on processor efficiency, flexibility, and resource utilization [1]- [3]. Because of the high flexibility of general-purpose processors and the high energy efficiency of specialized hardware, as shown in Figure 1, reconfigurable architecture has become an inevitable choice for addressing high-intensity applications [4]- [7].…”

Asap

“…Coarse-grained reconfigurable arrays (CGRAs), loosely defined as devices composed of multiple functional units (FUs) interconnected with an on-chip network that allows configuring the data path to accelerate a variety of computational patterns, are a promising class of accelerators for many domains, including high-performance computing (HPC) [11,31,40], edge devices, and multimedia [8,30,36,38,44]. All these areas benefit from the energy efficiency afforded by specialization, but also need adaptability to support complex applications composed of kernels [20,25,35,37] with very different behaviors and computational characteristics.…”