Argus: Low-Cost, Comprehensive Error Detection in Simple Cores

Hines, Stephen; Whalley, David; Tyson, Gary

doi:10.1109/micro.2007.18

Cited by 138 publications

(23 citation statements)

References 21 publications

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“…Additionally, Gizopoulos et al [57] provided a classification and a detailed study of existing online error detection techniques applied to multicore processor architectures. These approaches are classified into four main categories: redundant execution [58,59], periodic Built-In Self-Test (BIST) approaches [60], dynamic verification approaches [61,62], and anomaly detection approaches [63,64]. The results of this comparative study highlight the effectiveness of the dynamic verification approaches in targeting transient faults, permanent faults, and design bugs.…”

Section: Soc Monitoring and Diagnosismentioning

confidence: 92%

Incremental Modeling and Monitoring of Embedded CPU-GPU Chips

Djedidi

Djeziri

2020

Processes

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This paper presents a monitoring framework to detect drifts and faults in the behavior of the central processing unit (CPU)-graphics processing unit (GPU) chips powering them. To construct the framework, an incremental model and a fault detection and isolation (FDI) algorithm are hereby proposed. The reference model is composed of a set of interconnected exchangeable subsystems that allows it to be adapted to changes in the structure of the system or operating modes, by replacing or extending its components. It estimates a set of variables characterizing the operating state of the chip from only two global inputs. Then, through analytical redundancy, the estimated variables are compared to the output of the system in the FDI module, which generates alarms in the presence of faults or drifts in the system. Furthermore, the interconnected nature of the model allows for the direct localization and isolation of any detected abnormalities. The implementation of the proposed framework requires no additional instrumentation as the used variables are measured by the system. Finally, we use multiple experimental setups for the validation of our approach and also proving that it can be applied to most of the existing embedded systems.

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Section: Soc Monitoring and Diagnosismentioning

confidence: 92%

Incremental Modeling and Monitoring of Embedded CPU-GPU Chips

Djedidi

Djeziri

2020

Processes

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“…Evaluation is performed across 18 application benchmarks from the SPECINT2000 [22] and DARPA PERFECT [2] suites. Several insights resulted from this extensive exploration: accurate flip-flop level injection and layout (i.e., physical design) evaluation reveal many individual techniques provide minimal (less than 1.5×) SDC/DUE improvement (contrary to conclusions reported in the literature that were derived using inaccurate architecture-or software-level injection [20,36]), have high costs, or both. The consequence of this revelation is that most cross-layer combinations have high cost.…”

Section: Cross-layer Resilience Exploration With Clearmentioning

confidence: 99%

Cross-Layer Resilience Against Soft Errors: Key Insights

Mueller-Gritschneder

Cheng

Sharif

et al. 2020

Dependable Embedded Systems

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Driven by technology scaling, integrated systems become more susceptible to various causes of random hardware faults such as radiation-induced soft errors. Such soft errors may cause malfunction of the system due to corruption of data or control flow, which may lead to unacceptable risks for life or property in safety-critical applications. Hence, safety-critical systems deploy protection techniques such as hardening and redundancy at different layers of the system stack (circuit, logic, architecture, OS/schedule, compiler, software, algorithm) to improve resiliency against soft errors. Here, cross-layer resilience techniques aim at finding lower cost solutions by providing accurate estimation of soft error resilience combined with a systematic exploration of protection techniques that work collaboratively across the system stack. This chapter demonstrates how to apply the cross-layer resilience principle on custom processors, fixed-hardware processors, accelerators, and SRAM memories (with a focus on soft errors) and presents key insights obtained.

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“…This class of solutions, therefore, focuses on detecting hardware faults by monitoring for anomalous software behavior or symptoms. Much research has shown that such monitors (implemented in software and/or hardware) can be inexpensive and detect a wide range of hardware faults (Goloubeva et al, 2003; Pattabiraman et al, 2006; Wang and Patel, 2006; Dimitrov and Zhou, 2007; Meixner et al, 2007; Racunas et al, 2007; Li et al, 2008b; Hari et al, 2009; Lyle et al, 2009). Moreover, this strategy treats hardware faults as analogous to software bugs, potentially leveraging software reliability techniques and further amortizing overheads.…”

Section: Error Prevention Detection and Recoverymentioning

confidence: 99%

Addressing failures in exascale computing

Snir

Wisniewski

Abraham

et al. 2014

The International Journal of High Performance Computing Applica

282

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We present here a report produced by a workshop on 'Addressing failures in exascale computing' held in Park City, Utah, 4-11 August 2012. The charter of this workshop was to establish a common taxonomy about resilience across all the levels in a computing system, discuss existing knowledge on resilience across the various hardware and software layers of an exascale system, and build on those results, examining potential solutions from both a hardware and software perspective and focusing on a combined approach.The workshop brought together participants with expertise in applications, system software, and hardware; they came from industry, government, and academia, and their interests ranged from theory to implementation. The combination allowed broad and comprehensive discussions and led to this document, which summarizes and builds on those discussions.

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Argus: Low-Cost, Comprehensive Error Detection in Simple Cores

Cited by 138 publications

References 21 publications

Incremental Modeling and Monitoring of Embedded CPU-GPU Chips

Incremental Modeling and Monitoring of Embedded CPU-GPU Chips

Cross-Layer Resilience Against Soft Errors: Key Insights

Addressing failures in exascale computing

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