Arithmetic pattern generators for built-in self-test

Optimal hardware pattern generation for functional BIST

“…To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee. DATE 2000, Paris, France © ACM 2000 1-58113-244-1/00/03 ...$5.00 [6] [7] [8]. This technique was named as Arithmetic BIST (ABIST) and is comprehensively described in [9].…”

“…[7] presents two computation methods for the initial values (a simulation-based and an analytic one) using a simple adder as arithmetic unit. [10] and [8] include a theoretical analysis of the use of various functional units mentioned above as STPG. Very often, the UUT has random pattern resistant faults, and applying random patterns does not provide sufficient fault coverage.…”

Bit serial pattern generation and response compaction using arithmetic functions

“…Again, since the test length for complete fault coverage depends on the initialization of the pattern generator, we tried 10 different, randomly chosen initial states and selected the best result. The bit serial generators need about the same number of patterns for complete fault coverage as the parallel LFSRs and the best of the parallel arithmetic generators studied in [18]. For each circuit, the bit serial pattern generator performing best is highlighted by bold-faced letters.…”

“…All the pattern generators presented in this paper were simulated and the produced patterns were applied to the non-redundant versions of the ISCAS-85 benchmark circuits [4]. These circuits were chosen because then a direct comparison with the bit parallel arithmetic pattern generators of [18] is possible. As a reference, also linear feedback shift registers configured with internal XORs were employed as pattern generators.…”

“…The data paths of processors and in particular circuits for digital signal processing often contain adders, subtracters, arithmetic logic units (ALUs), and multipliers that together with registers can be employed as pattern generators or response compactors. Arithmetic pattern generators that produce a whole pattern in every clock cycle have been proposed in [7,16,18]. These bit parallel pattern generators use different types of adders and subtracters in order to combine the contents of the accumulator register with an input value that is kept constant.…”