The paper esamines the potentialities of genetic algorithms (GA ' a) with respect to the development of high-level TPG's. It summarizes atfirst the most relevant test pattern genemtion techniques based on genetic algorithms (GA ' s ) . This analysis distinguishes the considered techniques with respect to the abstraction level of the design under test. I n particular, the effectiveness of gate-level GA-based TPG's is compared with the effectiveness of high-level CA-based TPG's. Differences are deeply investigated. They mainly concern the way genetic operators ezploit specific simulation information to heuristically guide the genetic evolution. Moreover, a functional testing fmmework is described and used to actually measure on high-level descriptions the effectiveness of sophisticated CA-based TPC's in comparison to mndom approaches. Results are reported on a variety of benchmnrks.
'1. INTRODUCTIONGA's [I] have been shown to he effective when solving search problems. In the area of test generation of VLSI designs, GA's have been adopted as TPG engines at gate level and high level (e.g., RTL and behavioral). Section 1.1 and 1.2 show their respective characteristics, which are summarized and compared in Section 1.3. Section 2 describes the proposed testing framework, which allows to compare the reviewed GA techniques.Experimental results, presented in Sect.ion 3, show evidences i n the use of GA's for high-level TPG.
GA's for Gate-level TestingGA's have been used at first as a framework for simulationbased test generation in 121 and [3]. Both techniques target gatelevel descriptions. The former adopt a logic simulator to evaluate the generated test sequences, thus the generated test sets have often a lower fault coverage than that generated by a deterministic test generat.or. The later targets only combinational circuits. The adopted crossover operator exploits problem specific knowledge, thus making hard to identify the real contribution of GA's independently from the adopted heuristics. The performance of the CRlS test generator [Z] has been improved in [4] by using a fault simulation procedure to evaluate the generated sequences. The fault coverage increases as well as the execution time. The adopted fitness function is defined as: vi,j I (Np -Np) I< a (1) where t,he symbol NF and NF represent the number of changes of suh-circuits i and j due to the application of a sequence of 'Research activity partially supported by the IST-2001-34607 SYXIBAD European Project. length R and a is an appropriate small integer value. Other effective solutions targeting synchronous circuits have been proposed in [5] and [6]. The latter represents an extension of the former work, where up to 64 faults have been targeted simultaneously. GA's are used to propagate the induced faulty values to the design primary outputs. These techniques are suitable only for designs with a reset state. The adopted fitness function is: p= 1 ,"=I where ny.te and nF.r are respectively the number of gates and flip-flops, 4 is the k-th vector of sequen...
