ARROW - A Generic Hardware Fault Injection Tool for NoCs

Abstract

TodaysNoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techniques and like the system itself, it has to be validated and tested. A vulnerable point of attack for faults in distribiuted systems like NoCs is certainly the interconnect. In this paper, we will give an overview about todays challenges in interconnect technology and potential resulting physical faults. Unfortunately, describing faults on the physical level is far too accurate and so it is necessary to abstract and to map all these faults to a logical level. In more complex systems, also the logical level may become too detailed. As a result, an even more abstract layer, which is defined as the functional level, has to be introduced. To be able to verify fault tolerance, an experiment based test approach like fault injection is necessary. Arrow is a generic hardware fault injection tool, written in the hardware description language VHDL, especially designed for digital fault injection on the interconnect of NoCs, making use of fault models from the logical level. 1

Fault-Tolerant Networks-on-Chip Routing With Coarse and Fine-Grained Look-Ahead

“…They can provide a comprehensive analysis for the CG and FG algorithms from low to high fault rates; and are also consistent with previous work [20], [31]. The faults are injected to the NoC interconnect using a fault injector [34]. Similar to [3], [20], ten fault patterns are chosen for each fault rate and the average value is used as the result.…”

Flattening: An efficient approach to improving the performance of conventional MINs

“…In previous studies [30][31][32] simulators based on hardware definition language have been applied. Digital design tools such as Synopsys DC, Quartus, and Leonardo report parameters such as power consumption and area.…”