ASAP: A Speculative Approach to Persistence

Yadalam, Sujay; Shah, Nisarg; Yu, Xiangyao; Swift, Michael M.

doi:10.1109/hpca53966.2022.00070

Cited by 12 publications

(2 citation statements)

References 36 publications

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“…Thus, many authors [3]- [8] employ SimPoint [2], which defines application-specific simulation intervals, whereas other authors [9]- [12] choose to perform an initial fast forwarding or warm up of a determined number of instructions followed by a detailed simulation of a fixed number of subsequent instructions (both processes -forwarding and detailed simulation-are not application-specific and imply the same number of instructions for all evaluated benchmarks). This diversity also exists in the simulator employed (gem5 [13] in [4], [5], [7], [11], [14], Sniper [15] in [9], [16], or Scarab [17] in [6], [18], among others), the benchmarks used and the input data these applications receive (e.g., in the case of SPEC CPU suites, reference inputs in [3], [4], [7], [18], [19], test inputs in [16] or train inputs in [20]). Our motivational hypothesis in this work is that the particular simulation window employed when evaluating microarchitectural proposals related to the last level cache (LLC), such as cache replacement policies, can lead to incorrect conclusions.…”

Section: Introductionmentioning

confidence: 99%

Improving the Representativeness of Simulation Intervals for the Cache Memory System

Bueno,

Castro,

Pinuel

et al. 2024

IEEE Access

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Accurate simulation techniques are indispensable to efficiently propose new memory or architectural organizations. As implementing new hardware concepts in real systems is often not feasible, cycleaccurate simulators employed together with certain benchmarks are commonly used. However, detailed simulators may take too much time to execute these programs until completion. Therefore, several techniques aimed at reducing this time are usually employed. These schemes select fragments of the source code considered as representative of the entire application's behaviour -mainly in terms of performance, but not plenty considering the behaviour of cache memory levels-and only these intervals are simulated. Our hypothesis is that the different simulation windows currently employed when evaluating microarchitectural proposals, especially those involving the last level cache (LLC), do not reproduce the overall cache behaviour during the entire execution, potentially leading to wrong conclusions on the real performance of the proposals assessed. In this work, we first demonstrate this hypothesis by evaluating different cache replacement policies using various typical simulation approaches. Consequently, we also propose a simulation strategy, based on the applications' LLC activity, which mimics the overall behaviour of the cache much closer than conventional simulation intervals. Our proposal allows a fairer comparison between cache-related approaches as it reports, on average, a number of changes in the relative order among the policies assessed -with respect to the full simulation-more than 30% lower than that of conventional strategies, maintaining the simulation time largely unchanged and without losing accuracy on performance terms, especially for memory-intensive applications.

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Section: Introductionmentioning

confidence: 99%

Improving the Representativeness of Simulation Intervals for the Cache Memory System

Bueno,

Castro,

Pinuel

et al. 2024

IEEE Access

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“…Intel introduced more efficient cache line flush instructions (e.g., clwb) to substitute the legacy clflush [23,29,68]. Cache line flush enables programmers to flush modified cache lines to the persistence domain, in which data can be deemed to be persistent upon a power outage [13,24,68,84]. The concept of persistence domain was initially linked to the feature of Asynchronous DRAM Refresh (ADR).…”

Section: Introductionmentioning

confidence: 99%

Enabling Atomic Durability for Persistent Memory with Transiently Persistent CPU Cache

Ye¹,

Chen²,

Jiang³

et al. 2022

Preprint

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Persistent memory (pmem) products bring the persistence domain up to the memory level. Intel recently introduced the eADR feature that guarantees to flush data buffered in CPU cache to pmem on a power outage, thereby making the CPU cache a transient persistence domain. Researchers have explored how to enable the atomic durability for applications' in-pmem data. In this paper, we exploit the eADR-supported CPU cache to do so. A modified cache line, until written back to pmem, is a natural redo log copy of the in-pmem data. However, a write-back due to cache replacement or eADR on a crash overwrites the original copy. We accordingly develop Hercules, a hardware logging design for the transaction-level atomic durability, with supportive components installed in CPU cache, memory controller (MC), and pmem. When a transaction commits, Hercules commits on-chip its data staying in cache lines. For cache lines evicted before the commit, Hercules asks the MC to redirect and persist them into inpmem log entries and commits them off-chip upon committing the transaction. Hercules lazily conducts pmem writes only for cache replacements at runtime. On a crash, Hercules saves metadata and data for active transactions into pmem for recovery. Experiments show that, by using CPU cache for both buffering and logging, Hercules yields much higher throughput and incurs significantly fewer pmem writes than state-of-the-art designs.

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Ensuring SFENCE Instruction Correctness: A Formal Verification Framework Based on Invariants

Ponugoti

2024

2024 IEEE International Conference on Electro Information Technology (eIT)

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ASAP: A Speculative Approach to Persistence

Cited by 12 publications

References 36 publications

Improving the Representativeness of Simulation Intervals for the Cache Memory System

Improving the Representativeness of Simulation Intervals for the Cache Memory System

Enabling Atomic Durability for Persistent Memory with Transiently Persistent CPU Cache

Ensuring SFENCE Instruction Correctness: A Formal Verification Framework Based on Invariants

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