ASIC and FPGA implementation strategies for Model Predictive Control

Knagge, G.; Wills, Adrian; Mills, Adam J.; Ninness, Brett

doi:10.23919/ecc.2009.7074394

Cited by 28 publications

(17 citation statements)

References 17 publications

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“…Existing work on hardware implementation of optimization solvers can be grouped into those that use interior-point methods [2]- [4] and those that use active-set methods [5], [6]. The major difference is that our approach can efficiently handle optimization problems that are several orders of magnitude larger than what has been presented in previous works.…”

Section: Introductionmentioning

confidence: 85%

FPGA implementation of an interior point solver for linear model predictive control

Jerez

Constantinides

Kerrigan

2010

2010 International Conference on Field-Programmable Technology

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Abstract-Automatic control, the process of measuring, computing, and applying an input to control the behaviour of a physical system, is ubiquitous in engineering and industry. Model predictive control (MPC) is an advanced control technology that has been very successful in the chemical process industries due to its ability to handle large multiple input multiple output (MIMO) systems with physical constraints. It has recently been proposed to be applied to higher bandwidth systems, which add the requirement of greater sampling frequencies. The main hurdle is the need to solve a computationally intensive quadratic programming (QP) problem in real-time. In this paper we address the need for acceleration by proposing a highly efficient floating-point field-programmable gate array (FPGA) implementation that exploits the parallelism opportunities offered by interior-point optimization methods. The approach yields a 5x improvement in latency and a 40x improvement in throughput for large problems over a software implementation. This work builds on a previous FPGA implementation of an iterative linear solver, an operation at the heart of the interior-point method.

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Section: Introductionmentioning

confidence: 85%

FPGA implementation of an interior point solver for linear model predictive control

Jerez

Constantinides

Kerrigan

2010

2010 International Conference on Field-Programmable Technology

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“…This paper is concerned with facilitating applications of MPC in which computational complexity, in particular computation time, is likely to be an issue. One can foresee that applications to embedded systems, with the MPC algorithm implemented in a chip or an FPGA [5,13,14,17], are likely to run up against this problem.…”

Section: The Basic Ideamentioning

confidence: 99%

Multiplexed model predictive control

et al. 2012

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This paper proposes a form of MPC in which the control variables are moved asynchronously. This contrasts with most MIMO control schemes, which assume that all variables are updated simultaneously. MPC outperforms other control strategies through its ability to deal with constraints. This requires online optimization, hence computational complexity can become an issue when applying MPC to complex systems with fast response times. The multiplexed MPC scheme described in this paper solves the MPC problem for each subsystem sequentially, and updates subsystem controls as soon as the solution is available, thus distributing the control moves over a complete update cycle. The resulting computational speed-up allows faster response to disturbances, which may result in improved performance, despite finding sub-optimal solutions to the original problem.

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“…Existing work on hardware implementation of optimization solvers can be grouped into those that use interior-point methods [21]- [24] and those that use active-set methods [25], [26]. The suitability of each method for FPGA implementation was studied in [27], highlighting the advantages of interior-point methods for large problems.…”

Section: Related Workmentioning

confidence: 99%

“…However, we will show that if the structure of the QPs arising in MPC is taken into account, we can reach different conclusions as to the location of the computational bottleneck. The hardware implementation of sequential quadratic programming for nonlinear MPC was considered in [25], where the sources of parallelism in an active-set method were identified. The trade-off between data wordlength, computational speed and quality of the applied control was explored in an experimental manner.…”

Section: Related Workmentioning

confidence: 99%

Model predictive control for deeply pipelined field-programmable gate array implementation: algorithms and circuitry

Jerez

Ling

Constantinides

et al. 2012

IET Control Theory Appl.

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Model predictive control (MPC) is an optimization-based scheme that imposes a real-time constraint on computing the solution of a quadratic programming (QP) problem. The implementation of MPC in fast embedded systems presents new technological challenges. In this paper we present a parameterized field-programmable gate array (FPGA) implementation of a customized QP solver for optimal control of linear processes with constraints, which can achieve substantial acceleration over a general purpose microprocessor, especially as the size of the optimization problem grows. The focus is on exploiting the structure and accelerating the computational bottleneck in an existing primal-dual interior-point method. We then introduce a new MPC formulation that can take advantage of the novel computational opportunities, in the form of parallel computational channels, offered by the proposed pipelined architecture to improve performance even further. This highlights the importance of the interaction between the control theory and digital system design communities for the success of MPC in fast embedded systems.

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ASIC and FPGA implementation strategies for Model Predictive Control

Cited by 28 publications

References 17 publications

FPGA implementation of an interior point solver for linear model predictive control

FPGA implementation of an interior point solver for linear model predictive control

Multiplexed model predictive control

Model predictive control for deeply pipelined field-programmable gate array implementation: algorithms and circuitry

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