ASIC implementation of 64-bit comparator using reversible logic

Saranya, T.; Mallikarjunan, P.; Rajadurai, M. J.; Saranya, K.

doi:10.1109/iciiecs.2017.8275855

Cited by 2 publications

(1 citation statement)

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“…The works are evaluated in terms of application, design abstraction level and availability of information about physical implementation. A number of works propose reversible design of ALU components including adders/subtractors, magnitude comparators, multipliers and shifters and so on [14][15][16][17]. Reversible sequential circuits and memories have also been proposed [18][19][20][21].…”

Section: Literature Reviewmentioning

confidence: 99%

LDPC check node implementation using reversible logic

Awais

Razzaq

Ahmed

et al. 2019

IET Circuits, Devices & Systems

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Reversible logic is an emerging digital design paradigm which promises low energy dissipation; thanks to its information-lossless nature. True potential of this exciting concept can only be assessed by facing the design of practical complexity applications. Low density parity check (LDPC) decoding is one such application from forward error correction domain. The core of LDPC decoding is the check node (CN) processor, which executes the decoding algorithm and constitutes a major portion of decoder's overall power consumption. This work proposes a low-power LDPC CN architecture using reversible logic gates. Transistor level design and full custom layout of proposed architecture is carried out on UMC 90 nm complementary metal-oxide-semiconductor technology. All reversible blocks of proposed CN are optimised for quantum cost, garbage outputs and transistor count. The CN functionality is validated with post-layout simulations, layout versus schematic checks and design rule checks. The proposed CN occupies a post-layout area of 0.013 mm 2 , achieves up to 4.3 GHz frequency and consumes 52 μW power. The performance of proposed CN is also compared with its implementation using irreversible gates. The proposed CN achieves about 300% reduction in power delay product with affordable complexity as compared to its classical implementation.

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