ASIC implementation of fractionally spaced Rake receiver for high data rate UWB systems

Abstract

An ASIC implementation scheme of a fractionally spaced Rake (FS-Rake) receiver is presented for high data rate UWB systems to save hardware resources and avoid routing congestion. In this scheme, one pre-combining module and two stages of shift register and multiplexer are employed for multipath selection. ASIC implementation results demonstrate that the proposed scheme can save 13.1% cell area compared with the conventional FS-Rake structure. More importantly, routed nets are reduced by 37.2%. Therefore, serious routing congestion that is an obstacle to design convergence is mitigated effectively in this proposed scheme.Introduction: In ultra-wideband (UWB) systems, the Rake receiver that can provide diversity gain in multipath fading channels is always attractive for signal detection [1]. A fractionally spaced Rake (FS-Rake) can capture more energy and is much less sensitive to synchronisation errors, thus it achieves better performance than other Rake receivers [2, 3]. However, this high resolution FS-Rake costs higher hardware resources. In Rake implementation, shift registers and multiplexers are commonly utilised for multipath selection [4]. According to the UWB long spread delay channel conditions [5], the stage number of shift registers in a FS-Rake may be as large as several hundred to ensure that all the multipath components have fallen into the desired span. Moreover, in high data rate UWB systems, the stringent timing constraint and huge number of routed nets between shift registers and multiplexers can cause serious routing congestion and even result in design unconvergence. To solve these problems, a novel FS-Rake structure with one pre-combining module and a two-stage multipath selection part is proposed for ASIC implementation of high data rate UWB systems.

Add-select-delay-compare Viterbi decoder for UWB communications in electronic power systems

“…To verify the architecture initially, we implement the proposed VD (M = 64 and L = 9) for 500 Mbps single carrier UWB (SC-UWB) [14], [15] systems in Xilinx Virtex-6 evaluation board, which had up to 303 Mb/s throughput at 303 MHz. After the verification, it was then synthesized via using Synopsys design tools and TSMC .13 μm COMS technology optimized for 1.2 V supply voltage.…”

Introduction of SC-UWB proposal

“…iv) Adopting RAKE [13] [14] and equalization to combat inter-symbol interference (ISI), rather than OFDM combined with interleaving and codec. When the bandwidth is 500 MHz, there are actually only a few resolvable multipath components according to our measured results.…”