Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

Zhan, Cheng; Tzeng, Pei-Jer; Lau, John H.; Dai, Ming-Ji; Chien, Heng-Chieh; Lee, Ching-Kuan; Wu, Shaocheng; Kao, Kuo‐Shu; Huang, Shin-Yi; Fan, Chia-Wen; Chung, Seungjun; Huang, Yu-Wei; Lin, Yu-Min; Chang, Jung‐Wei; Yang, Tsun-Hua; Chen, Tai-Hung; Lo, R.; Kao, Ming-Jer

doi:10.1109/ectc.2012.6248883

Cited by 20 publications

(4 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The most significant advantage of the proposed fabrication flow is that an intact TSV insulation layer with excellent integrity and conformity can be obtained, resulting in an ultra-low leakage current. As shown in figure 4(a), there are three common types of insulation defects that are prone to occur during the conventional interposer manufacturing process, which will lead to three different TSV leakage modes [21,22]. The first type of defect is caused by Cu overburden CMP, this will lead to a short circuit between the Si substrate and the frontside RDL.…”

Section: Fabricationmentioning

confidence: 99%

See 1 more Smart Citation

Fabrication and characterization of a low-cost interposer with an intact insulation layer and ultra-low TSV leakage current

Luo

Wang

Sun

et al. 2018

J. Micromech. Microeng.

View full text Add to dashboard Cite

The application of a Si interposer is hindered by its complicated manufacturing process, high cost and some reliability challenges such as through silicon via (TSV) leakage. In this paper, a fabrication approach using a Si interposer is proposed, which can simplify the manufacturing process significantly and reduce the cost by more than 40%. Benefiting from the simplified process, the TSV insulation layer stays intact during the whole manufacturing process, an ultra-low TSV leakage current can be obtained. To evaluate the performance and reliability of the interposer, test samples consisting of 136 TSVs are designed and fabricated. A series of tests are carried out to verify the electrical insulating performance and reliability of the interposer. Under the bias voltage of 5 V, the TSV leakage current is 2.05 × 10−14 A, which is much lower than the usual value in the range of 10−12–10−9 A. The yield of daisy chains exceeds 91.66% and that of individual TSVs is more than 99.91%. All the interposer samples have successfully passed the thermal cycle test, and the resistance variation of each individual pathway is within 5% after 200 cycles.

show abstract

Section: Fabricationmentioning

confidence: 99%

“…insulation layer damage caused by Cu overburden CMP, Cu-Si short circuit occurred in backside TSV reveal). Some improved techniques have been developed to offer a better insulation layer [20][21][22][23]. However, these techniques make the manufacturing process more complicated, and it is still very hard to avoid the defects completely.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and characterization of a low-cost interposer with an intact insulation layer and ultra-low TSV leakage current

Luo

Wang

Sun

et al. 2018

J. Micromech. Microeng.

View full text Add to dashboard Cite

show abstract

“…Next is chip-to-wafer (C2W) bonding, for example [18,19], i.e., the micro bumped memory chip is bonded (either by natural reflow or thermal compression) to the TSV wafer with the carrier. After face-to-back C2W bonding, the carrier wafer is debonded from the TSV wafer.…”

Section: Fig 3 Critical Steps and Ownerships For (Face-to-face) Widementioning

confidence: 99%

Supply chains for 3D IC integration manufacturing

Lau

2012

2012 14th International Conference on Electronic Materials and Packaging (EMAP)

Self Cite

View full text Add to dashboard Cite

show abstract

“…This test vehicle can be degenerated to the case of: (a) wide I/O memory if there is not the memory-chip stacking nor the TSVs in the mechanical/thermal chips and the interposer is either an logic, microprocessor, or SoC; (b) wide I/O DRAM if there are not mechanical and thermal chips and the interposer is a logic chip; and (c) wide I/O interface ifthere is not the memory-chip stacking and there is not any TSV in the thermal/ mechanical chips. Thus, the core enabling technologies (such as via etching, dielectric, barrier and seed layers deposition, via filling, CMP, thin-wafer handling, electrical and thermal design and test of TSVs, wafer bumping of ultra finepitch lead-free microbumps, fluxless C2W bonding, electronmigration of microbumps, and reliability of microbump assemblies) developed[19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36] with this test vehicle are very useful and can have very broad applications.…”

mentioning

confidence: 99%

Recent Advances and New Trends in Nanotechnology and 3D Integration for Semiconductor Industry

Lau

2012

ECS Trans.

Self Cite

View full text Add to dashboard Cite

"There's Plenty of Room at the Bottom" is the title of Richard Feynman's lecture on December 29th, 1959 to the American Physical Society at California Institute of Technology (Caltech) and is generally considered to be the very first speech about nanotechnology. Some important milestones of nanotechnology will be briefly mentioned and the emphasis is placed on the applications and outlooks of nanotechnology in electronics. "Computing Machines in the Future" is the title of the Nishina Memorial Lecture at Gakushuin University in Tokyo given by the 1965 Nobel Physics Laureate, Richard Feynman on August 9th, 1985. During the lecture, Feynman not only told us to go for 3D integration, but also taught us how to do it! In this study, 3D integration will be the focus and the emphasis is placed on 3D IC integration and their recent advances and new trends. 3D Si integration will be briefly discussed

show abstract

Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

Cited by 20 publications

References 12 publications

Fabrication and characterization of a low-cost interposer with an intact insulation layer and ultra-low TSV leakage current

Fabrication and characterization of a low-cost interposer with an intact insulation layer and ultra-low TSV leakage current

Supply chains for 3D IC integration manufacturing

Recent Advances and New Trends in Nanotechnology and 3D Integration for Semiconductor Industry

Contact Info

Product

Resources

About