Assertion-based verification of a 32 thread SPARC™ CMT microprocessor

Turumella, B.; Sharma, Mukesh

doi:10.1145/1391469.1391535

Cited by 6 publications

(9 citation statements)

References 7 publications

(18 reference statements)

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“…In the worst case, the automaton can be exponential in the size of the property and the overhead of checking the property during simulation can be prohibitively expensive. In [24], it is reported that depending on the number and the kind of properties they express, property checking can degrade simulation speed anywhere from 25% to 100%.…”

Section: Discussion and Related Workmentioning

confidence: 99%

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An Efficient Runtime Validation Framework based on the Theory of Refinement

Jain¹,

Manolios²

2017

Preprint

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We introduce a new methodology based on refinement for testing the functional correctness of hardware and low-level software. Our methodology overcomes several major drawbacks of the de facto testing methodologies used in industry: (1) it is difficult to determine completeness of the properties and tests under consideration (2) defining oracles for tests is expensive and error-prone (3) properties are defined in terms of low-level designs. Our approach compiles a formal refinement conjecture into a runtime check that is performed during simulation. We describe our methodology, discuss algorithmic issues, and provide experimental validation using a 5-stage RISCV pipelined microprocessor and hypervisor.

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Section: Discussion and Related Workmentioning

confidence: 99%

“…This is undesirable. Furthermore, the effort to maintain properties for an industrial design can often be very large [24] and cannot be under estimated.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Runtime Validation Framework based on the Theory of Refinement

Jain¹,

Manolios²

2017

Preprint

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“…can be monitored using assertions [94]. Turumella et al explored how assertions can be used to verify the control logic of an enterprise-class chip-multi-threaded SPARC TM microprocessor [105].…”

Section: Control Logic Verificationmentioning

confidence: 99%

“…Pellauer explored interface assertions in Bluespec System Verilog [87]. Turumella et al 's work captured inter-module interface assertions in the SPARC TM microprocessor as well [105].…”

Section: Design Interfacementioning

confidence: 99%

“…While assertion-based validation of TLM/RTL models is applicable for all designs, there are eforts to explore assertion-based veriication speciic application scenarios. The paper [105] describes how dynamic ABV is used on the complex enterprise design of a 32-thread SPARC™ CMT microprocessor. It overcame most of the design veriication challenges such as exhaustive property checking.…”

Section: Dynamic Verification Using Simulationmentioning

confidence: 99%

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A Survey on Assertion-based Hardware Verification

et al. 2022

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Hardware verification of modern electronic systems has been identified as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware verification is to drastically reduce the validation and debug time without sacrificing the design quality. Assertion-based verification is a promising avenue for efficient hardware validation and debug. In this paper, we provide a comprehensive survey of recent progress in assertion-based hardware verification. Specifically, we outline how to define assertions using temporal logic to specify expected behaviors in different abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hybrid techniques. We conclude with a discussion on utilizing assertions for verifying both functional and non-functional requirements.

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An introduction to assertion-based verification

Tao

2009

2009 IEEE 8th International Conference on ASIC

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Assertion-based verification of a 32 thread SPARC™ CMT microprocessor

Cited by 6 publications

References 7 publications

An Efficient Runtime Validation Framework based on the Theory of Refinement

An Efficient Runtime Validation Framework based on the Theory of Refinement

A Survey on Assertion-based Hardware Verification

An introduction to assertion-based verification

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