Assessment of Au Stud-Solder Interconnection for Fine Pitch Flip Chip Packaging

Yeo, Anders; Lim, Suo Hon; Min, Tan Ai

doi:10.1109/eptc.2007.4469771

Cited by 3 publications

(1 citation statement)

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“…[12] Other approaches that have been studied are the use of either Au-to-Au ultrasonic bonding or Au-Stud-to-Solder bonding for the vertical interconnection. [13][14][15][16][17] Rapid reaction between Au and solder above the melting temperature of solder expels the oxide from the joint surface and eliminates the need of flux. The AuSn interconnect can thus be made using thermo-compression bonding at ambient.…”

Section: Introductionmentioning

confidence: 99%

Three dimensional interconnect using Au and pillar bumps

Kuo

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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Section: Introductionmentioning

confidence: 99%

Three dimensional interconnect using Au and pillar bumps

Kuo

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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Displacement-controlled coining of large arrays of gold stud bumps

Ozturk,

Yilmaz

2024

J. Micromech. Microeng.

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Novel, simple, and low-cost, displacement-controlled coining (DCC) process is developed for coining of gold stud bumps. A bottom mold made of aluminium which contains an array of geometrically well-defined cavities (nests) with known and pre-defined depth values in each nest, is designed and manufactured to adjust areas of coined surfaces and heights of coined stud bumps during sequential displacement-controlled coining processes. A double-side polished, and thick Borosilicate glass substrate is used as a flat surface to be in direct contact with the tails of the stud bumps to be coined. Above the double side polished glass substrate, another thick and rigid mold is positioned to uniformly apply the displacement-controlled deformation force to the stud bumps via the polished surface of the glass substrate. With the proposed displacement-controlled coining process, height and bonding surface area of the stud bumps can be tailored for flip-chip bonding (FCB) processes, especially when the maximum applicable force configuration of a FCB tool is limited (maximum of 20 N) during thermo-sonic flip chip bonding (TSFCB) processing. The proposed technique can be used to simultaneously coin arrays of stud bumps with high precision, providing an alternative, cost-effective, precise, time-efficient processing of stud bumps prior to TSFCB applications.

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