Assessment of Erase-Verify Function in NAND Arrays with Charge-Based Capacitance Measurement

Abstract

To accurately assess the reverse read function during erase verification (EV) in NAND products, a test structure of a NAND string accompanied with a charge-based capacitance measurement (CBCM) circuit is employed. The relationship between bit-line flipping voltage (V BL) and reverse read bias (V REV) is then established. The impact of erase threshold voltage (V T) distribution is also evaluated. Furthermore, this methodology is validated as the result of this test structure is consistent with that of a functional product.