Assigning program and data objects to scratchpad for energy reduction

Steinke, Stefan; Wehmeyer, Lars; Lee, Bo-Sik; Marwedel, Peter

doi:10.1109/date.2002.998306

Cited by 215 publications

(239 citation statements)

References 11 publications

Supporting

Mentioning

238

Contrasting

Order By: Relevance

“…Initially meant to reduce power consumption of an embedded device [28], today, scratchpads are advocated as means to increase a system's predictability. Similar to caches, scratchpads are small but fast memories located close to the processor.…”

Section: Related Workmentioning

confidence: 99%

Selfish-LRU: Preemption-aware caching for predictability and performance

Reineke

Altmeyer

Grund

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

View full text Add to dashboard Cite

Abstract-We introduce Selfish-LRU, a variant of the LRU (least recently used) cache replacement policy that improves performance and predictability in preemptive scheduling scenarios.In multitasking systems with conventional caches, a single memory access by a preempting task can trigger a chain reaction leading to a large number of additional cache misses in the preempted task. Selfish-LRU prevents such chain reactions by first evicting cache blocks that do not belong to the currently active task. Simulations confirm that Selfish-LRU reduces the CRPD (cache-related preemption delay) as well as the overall number of cache misses. At the same time, it simplifies CRPD analysis and results in smaller CRPD bounds.

show abstract

Section: Related Workmentioning

confidence: 99%

Selfish-LRU: Preemption-aware caching for predictability and performance

Reineke

Altmeyer

Grund

et al. 2014

2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

View full text Add to dashboard Cite

show abstract

“…At a finer granularity, program codes and operating systems are inspected. Energy-aware codes (e.g., Lorenz et al 2001) and memory organizations (e.g., Steinke et al 2002) are investigated. Measurements of different architectures and platforms are compared regarding their energy consumption.…”

Section: Engineering Approachesmentioning

confidence: 99%

Introduction to data mining for sustainability

Morik

Bhaduri

Kargupta

2011

Data Min Knowl Disc

View full text Add to dashboard Cite

“…Code allocation is performed at a function-level granularity. Our allocation method is based on the work in [2] where the allocation problem is formulated as the following knapsack problem. …”

Section: Code Allocation To Spmmentioning

confidence: 99%

“…The authors of [2] formulated the optimization problem to allocate program code to SPM as a 0/1 programming problem. They demonstrated the effectiveness of SPM against cache memory.…”

Section: Introductionmentioning

confidence: 99%

Energy efficiency of scratch-pad memory in deep submicron domains: an empirical study

Takase

Tomiyama

Zeng

et al. 2008

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:As the technology scales down to the deep submicron domain, the leakage energy in memory devices could contribute to a significant portion of the total energy consumption. Therefore, evaluation of energy consumption including the leakage energy is necessary. In this paper, we investigate the effectiveness of scratch-pad memory on energy reduction considering both the dynamic and leakage energy. The experiments are performed for 65 nm, 45 nm, and 32 nm technologies. The results demonstrate the effectiveness of scratch-pad memory in deep submicron technology. It is also observed that the leakage energy becomes less significant along with the technology scaling.

show abstract

Assigning program and data objects to scratchpad for energy reduction

Cited by 215 publications

References 11 publications

Selfish-LRU: Preemption-aware caching for predictability and performance

Selfish-LRU: Preemption-aware caching for predictability and performance

Introduction to data mining for sustainability

Energy efficiency of scratch-pad memory in deep submicron domains: an empirical study

Contact Info

Product

Resources

About