ASTEROID and the Replica-Aware Co-scheduling for Mixed-Criticality

Abstract

The ASTEROID project developed a cross-layer fault-tolerance solution to provide reliable software execution on unreliable hardware under soft errors. The approach is based on replicated software execution with hardware support for error detection that exploits future many-core platforms to increase reliability without resorting to redundancy in hardware. This chapter gives an overview of ASTEROID and then focuses on the performance of replicated execution and the proposed replica-aware co-scheduling for mixed-criticality. The performance of systems with replicated execution strongly depends on the scheduling. Standard schedulers, such as Partitioned Strict Priority Preemptive (SPP) and Time-Division Multiplexing (TDM)-based ones, although widely employed, provide poor performance in face of replicated execution. By exploiting co-scheduling, the replica-aware co-scheduling is able to achieve superior performance.

Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems

“…They have used replication besides re-execution (row 7). [31] has also presented a replica-aware co-scheduling method for MCSs by exploiting cross-layer fault tolerance mechanisms. This method has supported network-on-chip communication delay and replication management overheads.…”

“…The problem definition and motivational example are presented in Section IV. Then, in Section V, we describe the proposed Huang'14 [18], Ali'15 [23], Taherin'18 [24], Zhang'21a [25], Zhang'21b [26] (S)-Core ✓ ✓ ˆˆ✓ ˆˆ2 Haririan'15 [27], Digalwar'17 [28] (M)-Core ✓ ✓ ˆˆ✓ ˆˆ3 Ranjbar'19 [29], Ranjbar'21 [16] (M)-Core ✓ ✓ ✓ ✓ ✓ ˆˆ4 Ranjbar'22 [15] (M)-Core ✓ ✓ ✓ ✓ ˆ✓ ˆ5 Saraswat'09 [12], Saraswat '10 [13], Liu'13 [14], Al'16 [8], Alahmad'17 [30] (M)-Core ✓ ✓ ˆˆˆˆ✓ 6 Ranjbar'20 [9], Huang'14 [7], Al'16 [3] (S)-Core ✓ ✓ ✓ ˆˆ✓ ˆ7 Zeng'16 [2], Caplan'18 [11], Rambo'21 [31] (M)-Core ✓ ✓ ˆˆˆ✓ ˆ8 Koc'19 [32], Choi'18 [33] (M)-Core ✓ ✓ ✓ ˆˆ✓ ˆ9 Huang'11 [34] (M)-Core ✓ ˆˆˆˆˆˆ✓ 10 Das'14 [35] (M)-Core…”

“…). If function LPP MC Map() maps the subset sc, Algorithm 1 tests the schedulability and updates the RPM (lines[22][23][24][25][26][27][28][29][30][31][32][33][34][35]. If map suc is set (line 22), function Calculate U MC() tests the schedulability for provided mapping (line 23).…”

Online DVFS using Deep Learning: Sequence to Sequence LSTM Networks with Attention

“…The upper part of the curve (dark) shows the probability distribution of its execution time, and lower part (shaded in pink) shows the actual observed and measured execution time. It is evident from the figure, that the worst case execution time constitutes a minor part (tail) of this Gaussian curve, of time axis in nanoseconds to milliseconds (which is the order of execution time of one task).Authors in [28] extracted the execution times from Mibench automotive and security applications by running with small input on a dual core processor, and the WCET for basicmath application derived was 32.48ms. Execution of the tasks depends upon many factors like type of input, type of processor and cores, caches and branches of the program, and many more.…”

“…This is followed by computation of context vector as the weighted sum of annotations (line 26). This context vector is fed to the decoder along with previous hidden state and previous output of the decoder, to compute final output 𝑦 [𝑗] (lines [28][29]. The steps through calculation of attention scores through the computation of final outputs are carried for whole input sequence length.…”