Astute Approach to Handling Memory Layouts of Regular Data Structures

Šmelko, Adam; Kruliš, Martin; Kratochvíl, Miroslav; Klepl, Jiří; Mayer, Jiřı́; Šimůnek, Petr

doi:10.1007/978-3-031-22677-9_27

Cited by 2 publications

(1 citation statement)

References 17 publications

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“…In recent decades, a lot of work has been done on solving the problem of cache memory partitioning in the case of multiprocessor systems. Most of the solutions represent either techniques for sharing resources by logically dividing cache memories [16][17][18][19][20][21][22] or techniques for assigning cache memory partitions in the case where a system supports private cache memories [23][24][25][26]. Unfortunately, various techniques introduce problems of unfairness [27], so-called trashing [28], and quality of service problems [29].…”

Section: Existing Solutions and Their Analysismentioning

confidence: 99%

Scratchpad Memory Unit in Hybrid Control-flow and Dataflow Architectures

Korolija¹,

Štrbac-Savić²,

Đorđević³

2023

Proceedings of the International Scientific Conference - Sinteza 2023

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Dataflow architectures offer superior performance compared to control-flow architectures under certain conditions. This paper focuses on memory organization of a hybrid control-flow and dataflow architecture which guaranties that memory allocation can be accomplished in a predictable time. Mapping logical addresses into physical ones and accessing local memory in constant time is achieved using special address translation hardware. The memory organization is based on Buddy-system. It allows allocating arbitrary amounts of memory and prefetching data while it is being accessed by control-flow and dataflow hardware.

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