Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window

Zhenghua, Jiang; Xiao, Yi; Chatterjee, Swetaki; Mulaosmanovic, Halid; Duenkel, Stefan; Soss, S.; Beyer, Sven; Joshi, Rajiv V.; Chauhan, Yogesh Singh; Amrouch, Hussam; Narayanan, Vijaykrishnan; Ni, Kai

doi:10.1109/vlsitechnologyandcir46769.2022.9830172

Cited by 17 publications

(8 citation statements)

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“…The polarization in the FE modulates the V TH of the FeFET. The MW for the BG read (MW BG ) is given by [8]: where MW FG is the MW when FG is read, and γ BF is the body effect factor for the electrostatic coupling between FG and BG. γ BF is defined as the ratio of the equivalent series capacitance of BG, the channel, and the capacitance of the FG.…”

Section: Dual-port Ferroelectric Fetmentioning

confidence: 99%

“…Compared to the conventioanl single-port FeFET, where the memory states are read by applying a voltage to the Front gate (FG), dualport FeFET works by reading the memory states from the back gate (BG) of the transistor. This allows us to have a much larger MW (>10 ) due to the capacitive coupling of the FG and BG, as well as, improved retention and read-disturb free operation because of the separation of the read and write gates [6]- [8]. However, dual-port FeFET comes with its own challenges.…”

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confidence: 99%

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Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Kumar

Chatterjee

Thomann

et al. 2023

IEEE Trans. Circuits Syst. I

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Today's data-centric applications are incompatible with the predominant compute-centric computer architectures. The small on-chip memories of compute-centric computer architecture demand many energy-costly data transfers exposing the von-Neumann bottleneck. The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory (NVM) technology enabling novel data-centric architectures that go far beyond von-Nuemann principles. FeFETs are very promising for a wide range of applications starting from on-chip memories to in-memory computing and even neuromorphic computing. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as novel structure that offers for the first time disturb-free read operation along with > 10 larger memory window (MW) compared to conventional FeFETs. However, all of the before-mentioned types of variations are amplified in such a new structure. In this work, the impact of temperature variation is analyzed for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels and compared to conventional FeFET.We focus in our analysis on Hyperdimensional Computing (HDC), which is an emerging type of machine learning algorithm, that is being executed on top of FeFET-based in-memory circuits that perform efficient Hamming distance (i.e., similarity) computations. Through our cross-layer framework, we demonstrate the serious impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even HDC is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a crosslayer manner is indispensable.

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Section: Dual-port Ferroelectric Fetmentioning

confidence: 99%

mentioning

confidence: 99%

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Kumar

Chatterjee

Thomann

et al. 2023

IEEE Trans. Circuits Syst. I

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“…The dualport concept was proposed a decade ago 15−17 and has been revived recently on FeFET. 18,19 This structure shows two interesting properties. First, by properly designing a thick nonferroelectric dielectric layer, sensing through the read gate can amplify the memory window compared with that sensed through the write gate.…”

Section: ■ Introductionmentioning

confidence: 99%

“…First, by properly designing a thick nonferroelectric dielectric layer, sensing through the read gate can amplify the memory window compared with that sensed through the write gate. 18,19 The memory window amplification is interesting, for example, 4 V write voltage can induce a 10 V memory window, 18,19 and it needs further studies on the possibility of enabling low-voltage high-density memory. 20 Second, sensing through the read gate enables read disturb-free feature, which has been shown in multiple reports but has never been further elaborated.…”

Section: ■ Introductionmentioning

confidence: 99%

“…For a dual-port FeFET with an ultrathin channel, such as the FDSOI FeFET, the polarization programmed through the write gate modulates the channel carrier concentration, which can be also read out through the read gate leveraging the coupling of the two gates. The dual-port concept was proposed a decade ago − and has been revived recently on FeFET. , This structure shows two interesting properties. First, by properly designing a thick nonferroelectric dielectric layer, sensing through the read gate can amplify the memory window compared with that sensed through the write gate. , The memory window amplification is interesting, for example, 4 V write voltage can induce a 10 V memory window, , and it needs further studies on the possibility of enabling low-voltage high-density memory .…”

Section: Introductionmentioning

confidence: 99%

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Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET

Zhao,

Deng,

Chatterjee

et al. 2023

ACS Appl. Mater. Interfaces

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Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially in the high-threshold voltage (V TH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where the write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a nonferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high-V TH state, thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low-V TH state stability. Comprehensive theoretical and experimental validation has been performed on fully depleted silicon-on-insulator (FDSOI) FeFETs integrated on a 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the nonferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths.

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Temperature- and variability-aware compact modeling of ferroelectric FDSOI FET for memory and emerging applications

Chatterjee,

Kumar,

Gaidhane

et al. 2024

Solid-State Electronics

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Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window

Cited by 17 publications

References 0 publications

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET

Temperature- and variability-aware compact modeling of ferroelectric FDSOI FET for memory and emerging applications

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