Asymmetric ECC organization in 3D-memory via spare column utilization

Han, Hyunseung; Yang, Joon-Sung

doi:10.1109/dft.2015.7315128

Cited by 1 publication

(2 citation statements)

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“…The authors state that the flux of alpha particles generated from the Integrated Circuit (IC) plastic packaging material is almost ten times greater than that of the metallization layers, and the metallization layers block more than 30% of these particles before reaching an active layer; besides, only 0.4% of the particles can reach the active layer of a second die from the top. Thus, the lower layers of a 3D memory have lower error rates than the higher ones, which is an advantageous feature of 3D technologies [12][13][17] [18]. (c) (d)…”

Section: Soft Error Rate Analysis On 3d Memoriesmentioning

confidence: 99%

“…Chang, Huang, and Li [17] proposed an area and reliability-efficient ECC scheme for 3D RAMs, taking advantage of the shielding effect. Han and Yang [12] introduced a 3D memory scheme to ensure reliable operations by enhancing the ECC capacity of upper layer memories. Experimental results show that the proposed method can tolerate more than three times the bit The Hamming code is denoted as Ham(𝑛, 𝑘), where 𝑛, 𝑘 and 𝑟 are the numbers of bits of the codeword, data and redundancy, respectively.…”

Section: State-of-the-artmentioning

confidence: 99%

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LPC: An Error Correction Code for Mitigating Faults in 3D Memories

Freitas

Mota

Marcon

et al. 2021

IEEE Trans. Comput.

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The radiation sensitivity of memory cells increases dramatically as CMOS manufacture technology scales down; therefore, the reliability of memories has become a challenge. 3D technology has gained attention for having several advantages compared to the 2D counterpart, such as high integration density, high performance, low power, and high communication speed. Although several studies are targeting 3D memories, the effects on reliability using this technology have received little attention. This work introduces Line Product Code (LPC), a modified product code-based Error Correction Code (ECC) that uses both Hamming and parity in both rows and columns to implement reliable 3D memories. We implemented two lightweight LPC-based decoding algorithms in interleaved (LPCa-I) and non-interleaved (LPCa) versions, which allowed us to analyze LPC through a set of simulation cases that considers four severity levels of error incidence. The experimental results showed the effectiveness of the LPC-based algorithms, reaching correction rates of up 2.3 times higher compared to other Hamming-based algorithms.

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Section: Soft Error Rate Analysis On 3d Memoriesmentioning

confidence: 99%

Section: State-of-the-artmentioning

confidence: 99%