Asymmetric interactions in symmetric multi-core systems: Analysis, enhancements and evaluation

Scogland, Thomas R. W.; Balaji, .; Feng, Yong; Narayanaswamy,

doi:10.1109/sc.2008.5219748

Cited by 17 publications

(18 citation statements)

References 9 publications

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“…In order to investigate the causes, symptoms and treatments for such affinity problems we design the SyMMer [85] library discussed in Chapter 3. SyMMer exploits the fact that software is often as heterogeneous as the hardware on which it runs.…”

Section: Dimensions Of Localitymentioning

confidence: 99%

“…That said, the complexity of a single node of a distributed memory system has classically been relatively low, where each node consists of a number of homogeneous cores with only one or two coherent memory nodes and a relatively small difference in access latency (though even in these cases significant heterogeneity in performance can be observed [85]). …”

Section: A Modern Heterogeneous Node Architecturementioning

confidence: 99%

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Runtime Adaptation for Autonomic Heterogeneous Computing

Scogland

Feng

2014

2014 14th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing

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Heterogeneity is increasing across all levels of computing, with the rise of accelerators such as GPUs, FPGAs, and other coprocessors into everything from cell phones to supercomputers. More quietly it is increasing with the rise of NUMA systems, hierarchical caching, OS noise, and a myriad of other factors. As heterogeneity becomes a fact of life, efficiently managing heterogeneous compute resources is becoming a critical, and ever more complex, task. The focus of this dissertation is to lay the foundation for an autonomic system for heterogeneous computing, employing runtime adaptation to improve performance portability and performance consistency while maintaining or increasing programmability. We investigate heterogeneity arising from a myriad of factors, grouped into the dimensions of locality and capability. This work has resulted in runtime schedulers capable of automatically detecting and mitigating heterogeneity in physically homogeneous systems through MPI and adaptive coscheduling for physically heterogeneous accelerator based systems as well as a synthesis of the two to address multiple levels of heterogeneity as a coherent whole. We also discuss our current work towards the next generation of fine-grained scheduling and synchronization across heterogeneous platforms in the design of a highly-scalable and portable concurrent queue for many-core systems. Each component addresses aspects of the urgent need for automated management of the extreme and ever expanding complexity introduced by heterogeneity. I have also had the good fortune to collaborate with both Lawrence Livermore National Laboratory and Argonne National Laboratory. Experiences as an intern at each lab has had a significant effect on the final shape of my dissertation. Special thanks go to Dr. Pavan Balaji (again), Dr. Bronis de Supinski (again) and Dr. Barry Rountree. These collaborations proved to be major turning points for me, both in my research and my life as a whole.

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Section: Dimensions Of Localitymentioning

confidence: 99%

Section: A Modern Heterogeneous Node Architecturementioning

confidence: 99%

Runtime Adaptation for Autonomic Heterogeneous Computing

Scogland

Feng

2014

2014 14th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing

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“…The process images which form the executing environment for threads as well as a unit of parallel computation in modern operating systems, has its origins in the scheduling of multiprogrammed workloads in third-generation operating systems [92]. Over a shorter time span, Bode et al [20] measured job scheduling throughput on a 64-node cluster platform in 2000, while a 2008 work by Scogland et al [87] discusses thread scheduling on multicore processors, naming vendors with specific processor designs which will feature 64-way threading on a chip.…”

Section: Hybrid Models and Job-level Parallelismmentioning

confidence: 99%

Performance modeling of heterogeneous systems

Meyer

Elster

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

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As the complexity of parallel computers grows, constraints posed by the construction of larger systems require both greater, and increasingly non-linear, parameter sets to model their behavior realistically. These heterogeneous characteristics create a trade-off between the complexity and accuracy of performance models, creating challenges in utilizing them for design decisions.In this thesis, we take a bottom-up approach to realistically model software and hardware interactions, by composing system models from simpler, linear models, which allow parts of the analysis to be automated. We associate empirically benchmarked platform performance metrics with the core elements in a variant of bulk-synchronous execution, aiming to quantify application performance, and associated potential for computation and communication overlap on SMP clusters.The original bulk-synchronous performance model is introduced, and we identify areas of computation and communication where its abstractions impede realistic models of contemporary hardware. These are addressed independently, using experimental evidence to develop a representation collecting computation kernel characteristics and pairwise communications in matrices, to combine into a system model. As bulk-synchronous execution strongly depends on periodic, global synchronization, we develop a cost model for it by combining latency measurements with a parametric representation of signalling patterns, and experimentally verify the resulting predictions for three common algorithms.We describe a design to implement the BSPLib programming interface, combining threads and message-passing parallelism to achieve overlap on commodity cluster platforms, implementing its one-sided communication primitives using out-of-band control messages. We augment and validate the cost model of one adapted synchronization algorithm with the corresponding bandwidth requirement, completing a framework for modeling BSPLib program performance.Finally, we test the utility of this framework as a proof-of-concept for guiding software performance adaptations, using two cases. First, we use the latency terms to automatically generate synchronization operations, using model predictions to generate customized patterns with respect to platform topology, showing that the resulting algorithms equal or outperform the system defaults. Second, the strong scaling characteristics of a 5-point stencil code is compared for three implementations. Experiments show the performance overhead of our implementation, but also its capability for predicting program cost, including parameter values to optimize for balanced overlapping of computation and communication.ii Preface

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“…But we intend to pursue this problem in future. Existing work on dynamic processto-core mapping such as SyMMer framework proposed in [20] can be utilized by GePSeA.…”

Section: Accelerator To Core Mappingmentioning

confidence: 99%

GePSeA: A General-Purpose Software Acceleration Framework for Lightweight Task Offloading

Singh

Balaji

Feng

2009

2009 International Conference on Parallel Processing

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Hardware-acceleration techniques continue to be used to boost the performance of scientific codes. To do so, software developers identify portions of these codes that are amenable for offloading and map them to hardware accelerators. However, offloading such tasks to specialized hardware accelerators is non-trivial. Furthermore, these accelerators can add significant cost to a computing system. Consequently, this thesis proposes a framework called GePSeA (General Purpose Software Acceleration Framework), which uses a small fraction of the computational power on multicore architectures to offload complex application-specific tasks. Specifically, GePSeA provides a lightweight process that acts as a helper agent to the application by executing application-specific tasks asynchronously and efficiently. GePSeA is not meant to replace hardware accelerators but to extend them. GePSeA provide several utilities called core components that offload tasks on to the core or to the special-purpose hardware when available in a way that is transparent to the application. Examples of such core components include reliable communication service, distributed lock management, global memory management, dynamic load distribution and network protocol processing. We then apply the GePSeA framework to two applications, namely mpiBLAST, an open-source computational biology application and Reliable Blast UDP (RBUDP) based file transfer application. We observe significant speed-up for both applications.

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Asymmetric interactions in symmetric multi-core systems: Analysis, enhancements and evaluation

Cited by 17 publications

References 9 publications

Runtime Adaptation for Autonomic Heterogeneous Computing

Runtime Adaptation for Autonomic Heterogeneous Computing

Performance modeling of heterogeneous systems

GePSeA: A General-Purpose Software Acceleration Framework for Lightweight Task Offloading

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