Asymmetrical Dead-Time Control Driver for Buck Regulator

Abstract

This brief presents an asymmetrical dead-time control driver (ASDTCD) for synchronous buck converter operating in the continuous conduction mode. Dead-time control is an important metric for improving the efficiency of switching mode power regulator. Without an additional circuit, the proposed ASDTCD can generate dead time by controlling the slope for the output signal of the driver. The proposed ASDTCD utilizes the transition between triode region and saturation region for the power transistor to avoid body-diode conduction and shoot-through current while minimizing the switching loss. Thus, highspeed body-diode conduction sensor is avoided; thereby, reducing the power consumption and saving silicon area. In addition, the body-diode conduction time control accuracy is also enhanced. Less than 1-ns body-diode conduction time has been achieved without bringing in shootthrough current across 10-450-mA load range. With less than 0.5% of the total input power consumed, the proposed ASDTCD takes less than 1% of the power transistor area. This design is implemented in the 0.18-µm CMOS process.

High frequency and high efficiency DC-DC converter with sensorless adaptive-sizing technique

“…At light-load condition, DC-DC converter is often operated in discontinuous conduction mode (DCM) [24,25,26]. For DCM converter, the switching loss of power transistor P sw can be expressed as…”

A Current-Mode Four-Phase Synchronous Buck Converter With Dynamic Dead-Time Control

“…A simulated peak efficiency of 96.1% (94.2%) is obtained at a 1.8 V (1.2 V) output voltage, whereas the measured peak efficiency is decreased to 92.8% (91.8%). This is because of the inherent parasitic component effects of the bonding wires and PCB traces, particularly under low-voltage high-current conditions; for example, the load resistance R L is about 300 mΩ at 4.0 A load current with 1.2 V output voltage, whereas R trace can be as much as 20 mΩ [16], which indicates about 6.7% power loss, as in (14). Since the optimized dead-time is obtained with DDTC, the power efficiency is improved compared to the one without DDTC, particularly under medium and heavy load conditions.…”

“…Thus, the dead-time should be appropriately optimized. The optimal dead-time T DT _opt is heavily dependent on the load conditions, since the switching node voltage V SW is discharged by the inductor current [16], as in (2), which makes its optimization a challenging goal.…”

“…With a fixed dead-time gate driver, an adequate long dead-time is required for all load conditions, thereby resulting in a long body-diode conduction time under heavy load conditions, which greatly degrades the power efficiency. Therefore, numerous dead-time optimization methods have been reported to adaptively or dynamically adjust the dead-time, not only for improving the power efficiency [11]- [16], but also for helping the current balancing compensation [3], [17]. The sensorless optimization approaches in [3] and [11] are implemented with complex digital algorithms, which are not applicable to analog control-based power converters.…”

“…In [14] and [15], switched capacitors are applied for dead-time adjustment, which requires additional capacitors and switches, and the adjusted dead-time is employed in the next switching cycle. The asymmetrical dead-time control driver in [16] exhibits a compact structure that merges a dead-time controller with a gate driver for CCM operation. The dead-time is achieved by the designed asymmetrical rising (falling) slopes of the highside and low-side switches, which are heavily dependent on the supply voltage and process.…”