Asymmetry dual-LFSR reseeding for low power BIST

Ying, Jen-Cheng; Tseng, Wang-Dauh; Tsai, Wen-Jiin

doi:10.1016/j.vlsi.2017.10.012

Cited by 10 publications

(2 citation statements)

References 14 publications

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“…Therefore, effectively not only ensuring appropriate values for irrelevant items, but also having fewer conversions overall. This design overcomes the shortcomings mentioned earlier and effectively solves the two main problems facing the industry today: the increase in test data volume and power consumption will gradually increase in testing large integrated circuits [7]. To reduce the LFSR circuit's power dissipation, Fernandes R A, Rajan N. et al proposed power gating as a solution for reducing electricity leaking inside the circuit.…”

Section: Development Processmentioning

confidence: 99%

High-performance LFSR circuit design based on XOR gates

Xiao

2023

J. Phys.: Conf. Ser.

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The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.

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Section: Development Processmentioning

confidence: 99%

High-performance LFSR circuit design based on XOR gates

Xiao

2023

J. Phys.: Conf. Ser.

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“…To verify the correctness of hardware, testing is required. With the rapid development in semiconductor technology, the complexity of VLSI system increases exponentially [1,2]. Unfortunately, increase in circuit complexity also leads to complication in testing.…”

Section: Introductionmentioning

confidence: 99%

A Brief Review for Semiconductor Memory Testing Based on BIST Techniques

Singh¹,

Joshi²

2018

IJET

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With rapid growth of semiconductor industry and increase in complexity of semiconductor based memory, necessity of stringent testing methodology has become one of top most criteria for memory evaluation. This paper describes the fundamental concepts and overview of Built-In-Self-Test (BIST). It describes different functional faults modeling of RAM and flash memory. This review mentions about testing approaches for memory and illustrates BIST techniques for finding faults, power dissipation, area overhead and test time during testing, also includes research gap and future scope regarding the testing of memory.

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Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization

Thangam,

Manjith

2024

J Electron Test

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Asymmetry dual-LFSR reseeding for low power BIST

Cited by 10 publications

References 14 publications

High-performance LFSR circuit design based on XOR gates

High-performance LFSR circuit design based on XOR gates

A Brief Review for Semiconductor Memory Testing Based on BIST Techniques

Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization

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