AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation

Abstract

Binary tree topology generally fails to attract network on chip (NoC) implementations due to its low bisection bandwidth. Fat trees are proposed to alleviate this issue by using increasingly thicker links to connect switches towards the root node. This scheme is very efficient in interconnected networks such as computer networks, which use generic switches for interconnection. In an NoC context, especially for field programmable gate arrays (FPGAs), fat trees require more complex switches as we move higher in the hierarchy. This restricts the maximum clock frequency at which the network operates and offsets the higher bandwidth achieved through using fatter links. In this paper, we discuss the implementation of a binary tree-based NoC, which achieves better bandwidth by varying the clock frequency between the switches as we move higher in the hierarchy. This scheme enables using simpler switch architecture, thus supporting higher maximum frequency of operation. The effect on bandwidth and resource requirement of this architecture is compared with other FPGA-based NoCs for different network sizes and traffic patterns.

Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization

“…The evaluation of the projected model was accomplished in a 28 nm technology, wherein the authors achieved an efficient floor plan within 60 seconds. Vipin (2019) has introduced Fat trees for NoC implementations by alleviating the low bisection bandwidth problem. The authors have used highly thick links for interconnecting the switches and the root node.…”

“…With recent technological advancements, system design has expanded significantly, as well as the count of transistors on a chip has surpassed the range of possible combinations. As a consequence, Physical Design has become increasingly essential throughout the VLSI designing phase (Zhang et al 2020;Vipin 2019;. Floor planning seems to be the fundamental step in the Physical Design Flow process.…”

“…To deal with the rising complexity of architecture, hierarchical and IPbased components are utilized, making floor planning throughout the VLSI design cycle is increasingly realistic. Researchers have recently discovered the benefits of VLSI floor planning (Vipin 2019;Lin et al 2021a;Mohapatra et al 2020), particularly comprising a large number of chips. The architecture that must be recognized has been put together in floor planning, and specific space should indeed be allocated with different satisfactory limits to bring things close together, thereby reducing the dead space and cost incurred Sivaranjani and Senthil Kumar 2015).…”