Asynchronous cellular logic network as a co‐processor for a general‐purpose massively parallel array

Lopich, Alexey; Dudek, Piotr

doi:10.1002/cta.679

Cited by 16 publications

(8 citation statements)

References 23 publications

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“…For each voltage, the corresponding value of V SQ ij is obtained, enabling the least square fitting of Eq. (16). For 30 Monte-Carlo mismatch simulations at each process corner, the worst case occurs for the 'FF' corner, as depicted in Figure 12(a).…”

Section: Error Characterizationmentioning

confidence: 99%

“…Numerous low-level image processing primitives have been successfully implemented following this scheme: convolution filtering [6,7], programmable blurring [8], spatial [9] and temporal [10,11] contrast extraction, background subtraction [12], image compression [13], or high-dynamic range imaging [14] among others. Even academic [15,16] and commercial [17] general-purpose vision systems based on focal-plane processing have been reported.…”

Section: Introductionmentioning

confidence: 99%

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Bottom‐up performance analysis of focal‐plane mixed‐signal hardware for Viola–Jones early vision tasks

Fernández-Berni

Carmona-Galán

Rı́o

et al. 2014

Circuit Theory & Apps

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SUMMARYFocal-plane mixed-signal arrays have traditionally been designed according to the general claim that moderate accuracy in processing is affordable. The performance of their circuitry has been analyzed in these terms without a comprehensive study of the ultimate consequences of such moderate accuracy. In this paper, for the first time to the best of our knowledge, we do carry out this study. We move expectable performance of mixed-signal image processing hardware directly into the vision algorithm making use of it. This permits to close a wider design loop, enabling a more aggressive design of this kind of hardware provided that the algorithm, at the highest level-semantic interpretation of the scene-, can afford it. Thus, we present a thorough analysis of the non-idealities associated with the implementation of a QVGA array tailored for the distinctive characteristics of the Viola-Jones processing framework. The resulting deviation models are then introduced in the processing flow of this framework provided by the OpenCV library. We have found, contrary to what could be expected, that these deviations do not necessarily degrade the performance of the Viola-Jones algorithm. They could be even beneficial for certain high-level specifications. Additionally, we demonstrate the architectural advantages of our approach: exploitation of focal-plane distributed memory and ultra-low-power operation.

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Section: Error Characterizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Bottom‐up performance analysis of focal‐plane mixed‐signal hardware for Viola–Jones early vision tasks

Fernández-Berni

Carmona-Galán

Rı́o

et al. 2014

Circuit Theory & Apps

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“…The same team worked also on other complementary vision chips called ACLA (Asynchronous Cellular Logic Array) and ASPA (Asynchronous / Synchronous Processor Array). ACLA (Dudek, 2006;Lopich and Dudek, 2011) is an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image-processing algorithms. A proof-of-concept array of 2460 cells has been fabricated in a 0.35 µm CMOS process.…”

Section: <Insert Figure 4 Here>mentioning

confidence: 99%

Smart cameras on a chip: using complementary metal-oxide-semiconductor (CMOS) image sensors to create smart vision chips

Ginhac

2014

High Performance Silicon Imaging

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In this chapter, we introduce the fundamental concept of smart cameras on a chip or smart vision chips that simultaneously integrate on the same die image capture capability and highly complex image processing. Successive technology scaling has made possible the integration of specific processing elements designed at chip-level, at columnlevel or at pixel-level. To illustrate this continuous evolution, we survey three different categories of vision chips, exploring first the pioneering works on artificial retinas, then describing the most significant computational chips, and finally presenting the most recent image processing chips able to perform complex algorithms at a high frame rate.

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“…Unfortunately, CMOS/memristor hybrids are still just a promising solution, but they are not commercially available yet. Asynchronous realizations as that proposed in are also an option for LN communications in the implementation of global operations.…”

Section: Related Workmentioning

confidence: 99%

Split and shift methodology on cellular processor arrays: area saving versus time penalty

Fernandez

Brea

Cabello

2012

Circuit Theory & Apps

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This paper addresses the so-called split and shift methodology. This methodology deals with the implementation of kernels of sizes that go above the physically implemented resources (local connections and weighting circuits) on synchronous cellular processor arrays (CPA), including the realization of large neighborhood operations and/or the reduction of the available hardware in order to drop the area consumption. Two main goals are pursued in the development of the methodology, namely: (1) minimum penalty at processing time and (2) absolutely no penalty at functional level. The paper presents different techniques and guidelines for the methodology application and introduces a Figure of Merit to evaluate them by relating area gains with time penalty. This, along with a kernel shape analysis, led us to propose more adequate configurations of weighting circuits and to justify the classical choice of North-East-West-South connectivity. To validate the methodology, we realize several estimates over actual physical implementations, and we propose the realization over CPAs of the spin filters, scale invariant feature transform and speeded-up robust features algorithms. A more in-depth trade-off analysis is realized over the implementation of the pixel level snakes algorithm.but it can interact with separated PEs, thanks to the propagative effects of the array dynamics of kernel application. The basic characteristic of local connectivity and its simple SIMD control makes this kind of systems very suitable for hardware implementation. However, as a consequence, the natural size of the kernels to be applied is limited to the smallest one (3 Â 3). This is, on the other hand, an important limitation in the functionality of a CPA as larger neighborhoods are needed in several image processing primitives as diffusion or low-pass filtering operations [1], halftoning [2], texture analysis [3] or matching and hit&miss operations [4], some of them used in algorithms like modern scale-and rotation-invariant feature extractors like scale invariant feature transform (SIFT) and speeded-up robust features (SURF) [5,6].As indicated, a CPA can realize global processing taking into account the whole image information thanks to the propagative effects of the architecture. According to this we can think in solving the remote neighbors interaction through the recursive application of templates. In fact, a recursive process can be summarized in the application of a large neighborhood (LN) template. Nevertheless, the inverse process, the decomposition of a LN template into minimum-sized templates is not trivial, and different approaches have been developed to deal with this issue.The challenge is then to implement any kind of LN operations while keeping the local connectivity and with affordable penalties in performance. Our goal is to do it, in addition, with the minimum impact in the architecture at hardware level.On the other hand, on focal-plane processors with a pixel-to-PE assignment, the area occupation is not only a matter of cost or h...

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Asynchronous cellular logic network as a co‐processor for a general‐purpose massively parallel array

Cited by 16 publications

References 23 publications

Bottom‐up performance analysis of focal‐plane mixed‐signal hardware for Viola–Jones early vision tasks

Bottom‐up performance analysis of focal‐plane mixed‐signal hardware for Viola–Jones early vision tasks

Smart cameras on a chip: using complementary metal-oxide-semiconductor (CMOS) image sensors to create smart vision chips

Split and shift methodology on cellular processor arrays: area saving versus time penalty

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