Asynchronous circuit verification: From specification to circuit

Le-Huu, Khoi-Nguyen; Nguyen, Tin T.; Bui, Thang H.; Dinh-Duc, Anh-Vu

doi:10.1109/commantel.2013.6482432

Cited by 2 publications

(2 citation statements)

References 19 publications

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“…The formal verification for the data path and controller generation phase was proposed, and the finite state machine description and register transfer-operations were used. A system development life cycle (SDLC) method was presented [13] for the asynchronous circuit verification, the method can be used to describe the desired asynchronous circuit behaviors and refine those descriptions. The verification approach of digital circuits by using a lot of internal and external destabilizing factors was investigated [14], the destabilizing factors impact on the circuit operations was considered when the verification was carried out.…”

Section: Introductionmentioning

confidence: 99%

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

Zhang

Ling²,

Chen³

2014

TOEEJ

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Abstract:The VLSI technology has led to the increased complexity in hardward design, therefore the verification for the correctness of circuit operations has become an exrtremely important task. The verification procedure can be reduced by means of the equivalent signal lines in the circuits. In this paper, a new method is presented for determining the equivalent signal lines, the method utilizes the weight value assignment of signal lines in circuits. First of all, the method makes use of the topological information of circuits to perform forward weight value assignments, assign weight values to the signal lines from the primary inputs to primary outputs. Afterwards, carry out the backward weight value assignment, assign weight values to the signal lines from the primary outputs to primary inputs. Secondly, carry out the random pattern simulation to further check the equivalence of signal lines. A lot of experimental results show that the verification of digital circuits can be carried out effectively by using the method proposed in this paper, the time being needed for the verification procedure can be cut down by utilizing the equivalent signal lines.

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Section: Introductionmentioning

confidence: 99%

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

Zhang

Ling²,

Chen³

2014

TOEEJ

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“…Speedindependent asynchronous circuits are obtained from these nets via direct translation, that is, the control channel and some of the data channels are mapped directly to David unit control circuit. Paper [12] used a new kind of Petri net called PN-DFG as a bridge between the high-level behavior description and the logic gate level, and developed the PAiD tool to design and verify asynchronous circuits. In paper [13], Petri nets-based methods of modeling, analysis, verification and synthesis of asynchronous systems were introduced in detail.…”

Section: Introductionmentioning

confidence: 99%

Petri Net-based Modeling and VHDL Implementation of Digital Systems

Wan¹

2016

Proceedings of the 2016 International Conference on Computer Science and Electronic Technology

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Abstract-Petri net-based digital systems modeling and hardware implementation method is well-studied. However, the existing methods are mainly applied to synchronous circuits. In this paper, a new approach is proposed for the modeling and VHDL implementation of digital systems based on an extended class of Petri nets. The generalized synchronous self-modifying net (GSSN) is defined to describe digital systems. Based on a new kind of D flip-flop, known as multi-input & multi-clock D flipflop, the specific conversion algorithm from Petri nets models to VHDL codes is presented. A design example is given to illustrate the capabilities of the proposed approach. The approach presented in the paper is suitable for both asynchronous systems and synchronous systems.

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Asynchronous circuit verification: From specification to circuit

Cited by 2 publications

References 19 publications

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

Petri Net-based Modeling and VHDL Implementation of Digital Systems

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