Asynchronous design methodologies: an overview

Abstract

Asynchronous design has been an active area of research since at least the mid 1950's, but has yet to achieve widespread use. We examine the benefits and problems inherent in asynchronous computations, and in some of the more notable design methodologies. These include Huffman asynchronous circuits, burst-mode circuits, micropipelines, template-based and trace theory-based delay-insensitive circuits, signal transition graphs, change diagrams, and compilation-based quasidelay-insensitive circuits.

Diagrammatic Reasoning for Delay-Insensitive Asynchronous Circuits

“…On the other hand problems such as large silicone footprint and difficulties of fabrication hampered the adoption of asynchronous technology into the mainstream. These are just some of the well known advantages and disadvantages of the technology [1].…”

“…On the other hand problems such as large silicone footprint and difficulties of fabrication hampered the adoption of asynchronous technology into the mainstream. These are just some of the well known advantages and disadvantages of the technology [1].Another challenge raised by asynchronous design is that of reasoning about the correctness of circuits, and it has attracted a great deal of research interest. Several models of asynchronous circuits exists, such as Huffman [2] and burstmode circuits [3], which fall in the broader category of bounded-delay circuits, and delay-insensitive circuits, of which a notable version are the so-called micropipelines [4].…”

Asynchronous circuit design

“…Asynchronous design is not a single well-defined method, but rather a wide spectrum of options in a number of areas: handshake protocol, circuit implementation style, and theoretical basis for the design of control circuits [25]. In the following, the choice of handshaking protocol and circuit implementation style is addressed in the context of low power consumption.…”

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design

“…Two wires are used for a data encoded in FPDR encoding, and one wire for a request signal and an acknowledge signal. The proposed FPGA is based on Quasi-DelayInsensitive (QDI) model which assumes that gate delays and wire delays are unknown, and signal transitions occur at the same time at all end-points in wire forks [14], [15].…”