Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path

Xia, Zhengfan; Hariyama, Masanori; Kameyama, Michitaka

doi:10.1109/tvlsi.2014.2314685

Cited by 27 publications

(5 citation statements)

References 17 publications

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“…In this paper we used the 2-Phase dual rail protocol. In 2-Phase dual rail protocol, the data represented in the form of true and false [6].…”

Section: Revised Manuscript Received On October 15 2019mentioning

confidence: 99%

Performance of Asynchronous Queasy Delay Insensitive (QDI) Circuit Templates

Gimmadi,

Bhaskara

2019

IJEAT

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Asynchronous Queasy Delay Insensitive (QDI) is the more promising solution for the reducing the effect off power consumption due improvement in the fabrication technology. In literature there were proposed many QDI techniques but Precharged Half Buffer (PCHB), Autonomous Single Validate Half Buffer (ASVHB) and Sense Amplifier Half Buffer (SAHB) are efficient techniques. In this paper author implemented the templates of PCHB, ASVHB and SAHB. Simulation results are verified, and results are compared. From the result it is observed that SAHB will consume the less power and takes the less area for constructing the template when compare to other two methods.

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“…In this paper we used the 2-Phase dual rail protocol. In 2-Phase dual rail protocol, the data represented in the form of true and false [6].…”

Section: Revised Manuscript Received On October 15 2019mentioning

confidence: 99%

Performance of Asynchronous Queasy Delay Insensitive (QDI) Circuit Templates

Gimmadi,

Bhaskara

2019

IJEAT

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“…Many synchronous multipliers exist [1], and some non-robust [2][3][4][5][6][7][8][9][10][11][12], and few robust asynchronous multiplier designs [13][14][15][16] have been reported in the literature. References [2][3][4][5][6][7][8][9][10][11][12] discuss different asynchronous multiplier designs, which are either full-custom or semi-custom designs and make use of a non-robust, non-delay insensitive two-phase bundled-data asynchronous handshake protocol for data processing and communication. Although bundled-data asynchronous multipliers are likely to be better off than the synchronous multipliers due to the formers' ability to achieve average-case speed performance and low power compared to the worst-case speed performance of the latter, they are not robust.…”

Section: Introductionmentioning

confidence: 99%

Speed, energy and area optimized early output quasi-delay-insensitive array multipliers

2020

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Multiplication is a widely used arithmetic operation that is frequently encountered in microprocessing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive double-rail data encoding and four-phase return-to-zero (RTZ) handshaking and four-phase return-to-one (RTO) handshaking. In this context, this article makes two contributions: (i) the design of a new asynchronous partial product generator, and (ii) the design of a new asynchronous half adder. We analyze the usefulness of the proposed partial product generator and the proposed half adder to efficiently realize QDI array multipliers. When the new partial product generator and half adder are used along with our indicating full adder, significant reductions are achieved in the design metrics compared to the optimum QDI array multiplier reported in the literature. The cycle time is reduced by 17%, the area is reduced by 16.1%, the power is reduced by 15.3%, and the product of power and cycle time is reduced by 29.6% with respect to RTZ handshaking. On the other hand, the cycle time is reduced by 13%, the area is reduced by 16.1%, the power is reduced by 15.2%, and the product of power and cycle time is reduced by 26.1% with respect to RTO handshaking. Further, the RTO handshaking is found to be preferable to RTZ handshaking to achieve slightly improved optimizations in the design metrics. The QDI array multipliers were realized using a 32/28nm complementary metal oxide semiconductor (CMOS) process technology.

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“…Asynchronous multiplier designs have been discussed in the literature [6][7][8][9][10][11]. Some of these are full-custom i.e., transistor-level designs which do not utilize a standard digital cell library and/or the rest utilize the bundled-data handshake protocol for data communication between the current stage and next stage registers of an asynchronous circuit stage by combining single-rail input data with dedicated request and handshake wires.…”

Section: Introductionmentioning

confidence: 99%

Early Output Quasi-Delay-Insensitive Array Multipliers

et al. 2019

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Multiplication is a widely used arithmetic operation in microprocessing and digital signal processing applications, and multiplication is realized using a multiplier. This article presents the quasi-delay-insensitive (QDI) early output versions of recently reported indicating asynchronous array multipliers. Delay-insensitive dual-rail encoding is used for data representation and processing, and 4-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols are used for data communication. Many QDI array multipliers were realized using a 32/28 nm complementary metal oxide semiconductor (CMOS) technology. Compared to the optimum indicating array multiplier, the proposed optimum early output array multiplier achieves a 6.2% reduction in cycle time and a 7.4% reduction in power-cycle time product (PCTP) with respect to RTZ handshaking, and a 7.6% reduction in cycle time and an 8.8% reduction in PCTP with respect to RTO handshaking without an increase in the area. The simulation results also convey that the RTO handshaking is preferable to the RTZ handshaking for the optimum implementation of QDI array multipliers.

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Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path

Cited by 27 publications

References 17 publications

Performance of Asynchronous Queasy Delay Insensitive (QDI) Circuit Templates

Performance of Asynchronous Queasy Delay Insensitive (QDI) Circuit Templates

Speed, energy and area optimized early output quasi-delay-insensitive array multipliers

Early Output Quasi-Delay-Insensitive Array Multipliers

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