ATE test time reduction using asynchronous clock period

Venkataramani, Praveen; Agrawal, Vishwani D.

doi:10.1109/test.2013.6651931

Cited by 8 publications

(5 citation statements)

References 22 publications

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“…Recently, there have been some contributions in testing multi-core and many-core systems with advanced static and dynamic power management capabilities such as PCPG and DVFS. These efforts can be divided into two main categories 1) techniques which test the system including power switches to ensure that it properly works at different voltage-frequency settings [29] and 2) contributions in which associated hardware for power management is made use of to control power dissipation during the test process while reducing the TAT [30]. Most of the techniques in these two categories have been proposed for the offline testing process of DPM-based systems.…”

Section: Related Work and Motivationsmentioning

confidence: 99%

A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures

Haghbayan

Rahmani

Miele

et al. 2016

IEEE Trans. Comput.

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Aggressive technology scaling triggers novel challenges to the design of multi-/many-core systems, such as limited power budget and increased reliability issues. Today's many-core systems employ dynamic power management and runtime mapping strategies trying to offer optimal performance while fulfilling power constraints. On the other hand, due to the reliability challenges, online testing techniques are becoming a necessity in current and near future technologies. However, state-of-the-art techniques are not aware of the other power/ performance requirements. This paper proposes a power-aware non-intrusive online testing approach for many-core systems. The approach schedules software based self-test routines on the various cores during their idle periods, while honoring the power budget and limiting delays in the workload execution. A test criticality metric, based on a device aging model, is used to select cores to be tested at a time. Moreover, power and reliability issues related to the testing at different voltage and frequency levels are also handled. Extensive experimental results reveal that the proposed approach can i) efficiently test the cores within the available power budget causing a negligible performance penalty, ii) adapt the test frequency to the current cores' aging status, and iii) cover available voltage and frequency levels during the testing.

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Section: Related Work and Motivationsmentioning

confidence: 99%

A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures

Haghbayan

Rahmani

Miele

et al. 2016

IEEE Trans. Comput.

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“…This leads to long test time and high testing cost, especially for a large digital circuit whose scan test may contain millions or billions of clock cycles. A recent proposal of aperiodic test [17], [19] minimizes test time by dynamically adjusting the clock period to keep the power consumption at P max level in all clock cycles. Figure 4 illustrates our example of two cycles.…”

Section: Background On Multifrequency (Aperiodic)mentioning

confidence: 99%

“…For aperiodic test [17], [19], we customize each cycle with shortest possible period T i = E i /P max and the test time (T T aper ) becomes,…”

Section: Test Timementioning

confidence: 99%

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Few Good Frequencies for Power-Constrained Test

Gunasekar

Agrawal

2015

2015 28th International Conference on VLSI Design

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In the aperiodic clock testing method, power is kept at the specified limit by stretching or contracting the clock periods according to circuit activity. As reported, the test time of power constrained test can be reduced by 40-50%. Considering the capability of the test equipment and simplicity of test program, the number of clock periods should be kept low. In this paper, we give algorithms to find the optimum clock periods. Using the well known relation that the test time equals total energy for the entire test divided by the average power, the kthroot solution maximizes the average power for k test clocks and given maximum power constraint. This solution uses a piece-wise linear approximation for the sorted pseudo-energy profile of test cycles obtained from power estimation and timing analysis tools. For small k, the kth-root solution is optimized by a numerically efficient locally exhaustive search (LES) algorithm. Results show that close to maximum attainable test time reduction is achievable by as few as four to ten selected clocks.

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“…The idea of asynchronous testing was introduced at the LATW in 2012 [1]. Simulation results have shown the feasibility of this idea [9], [8]. Recent papers show that voltage reduction can increase the speed of power constrained synchronous testing [10], [11].…”

Section: Prior Workmentioning

confidence: 99%

A Test Time Theorem and its Applications

2014

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Abstract-We prove a theorem stating that the test time of digital test is obtained upon dividing the total energy dissipated during test by the average rate of consumption or power. As we try to reduce the test time, the critical path delay (structural constraint) and the peak power capability of the circuit (power constraint) limit our capability to increase the rate of energy consumption. The theorem leads to two modes of testing, namely, synchronous and asynchronous. Supply voltage plays a significant role in optimizing the test time.

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ATE test time reduction using asynchronous clock period

Cited by 8 publications

References 22 publications

A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures

A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures

Few Good Frequencies for Power-Constrained Test

A Test Time Theorem and its Applications

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