2022
DOI: 10.1039/d2ma00208f
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Atomic layer deposited tantalum silicate on crystallographically-oriented epitaxial germanium: interface chemistry and band alignment

Abstract: The interface chemistry and energy band alignment properties of atomic layer deposited (ALD) tantalum silicate (TaSiOx) dielectrics on crystallographically-oriented, epitaxial (001)Ge, (110)Ge, and (111)Ge thin-films, grown on GaAs substrates by...

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Cited by 3 publications
(2 citation statements)
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“…The integration of high-κ gate dielectrics such as HfO 2 and Al 2 O 3 on (100) and (110) crystal planes should not produce defects due to the effect of process temperature during deposition, rather only passivating the surface states and eliminating the interdiffusion of high-κ dielectric and channel materials. , Using these technologically important crystal planes, (100) and (110), from high electron and hole mobility Ge channel materials compared with Si along with a high-κ dielectric, one could make FinFET , or gate-all-around (GAA) NSFET for high-density and ultralow-power CMOS. However, the interfacial defects at the high-κ (e.g., HfO 2 ) and Ge channel material would require an interface passivation layer (IPL) to control the interface state density ( D it ). , An in situ ultrathin SiO 2 passivation layer from a tris( tert -butoxy)silanol (Si(OH)(OC-(CH 3 ) 3 ) 3 ) precursor during atomic layer deposited (ALD) gate dielectric or by a Si IPL layer and/or GeO x via thermal oxidation or by ozone oxidation was prescribed as IPL layer formation strategies for subsequent Al 2 O 3 and composite Al 2 O 3 /HfO 2 dielectrics deposition. In either case, the main objective was to reduce the D it at the high-κ/Ge heterointerface. Over the last two decades, surface recombination velocities (SRV) ≤ 1 cm/s were reported for Si, and ultralow SRV values were made possible by superior surface passivation with low D it ≈ 10 9 –10 12 eV –1 cm –2 . The extensive research on the surface passivation of Si with low D it over the decades has been transferred to p-Ge and n-Ge by several researchers. Noticeably, Berghuis et al have studied the surface passivation of bulk Ge using a combination of plasma-enhanced ALD (PEALD) and thermal ALD a-Si...…”
Section: Introductionmentioning
confidence: 99%
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“…The integration of high-κ gate dielectrics such as HfO 2 and Al 2 O 3 on (100) and (110) crystal planes should not produce defects due to the effect of process temperature during deposition, rather only passivating the surface states and eliminating the interdiffusion of high-κ dielectric and channel materials. , Using these technologically important crystal planes, (100) and (110), from high electron and hole mobility Ge channel materials compared with Si along with a high-κ dielectric, one could make FinFET , or gate-all-around (GAA) NSFET for high-density and ultralow-power CMOS. However, the interfacial defects at the high-κ (e.g., HfO 2 ) and Ge channel material would require an interface passivation layer (IPL) to control the interface state density ( D it ). , An in situ ultrathin SiO 2 passivation layer from a tris( tert -butoxy)silanol (Si(OH)(OC-(CH 3 ) 3 ) 3 ) precursor during atomic layer deposited (ALD) gate dielectric or by a Si IPL layer and/or GeO x via thermal oxidation or by ozone oxidation was prescribed as IPL layer formation strategies for subsequent Al 2 O 3 and composite Al 2 O 3 /HfO 2 dielectrics deposition. In either case, the main objective was to reduce the D it at the high-κ/Ge heterointerface. Over the last two decades, surface recombination velocities (SRV) ≤ 1 cm/s were reported for Si, and ultralow SRV values were made possible by superior surface passivation with low D it ≈ 10 9 –10 12 eV –1 cm –2 . The extensive research on the surface passivation of Si with low D it over the decades has been transferred to p-Ge and n-Ge by several researchers. Noticeably, Berghuis et al have studied the surface passivation of bulk Ge using a combination of plasma-enhanced ALD (PEALD) and thermal ALD a-Si...…”
Section: Introductionmentioning
confidence: 99%
“…However, the interfacial defects at the high-κ (e.g., HfO 2 ) and Ge channel material would require an interface passivation layer (IPL) to control the interface state density (D it ). 26,27 An in situ ultrathin SiO 2 passivation layer from a tris(tert-butoxy)silanol (Si(OH)(OC-(CH 3 ) 3 ) 3 ) precursor during atomic layer deposited (ALD) gate dielectric 28 or by a Si IPL layer and/or GeO x via thermal oxidation or by ozone oxidation was prescribed as IPL layer formation strategies for subsequent Al 2 O 3 and composite Al 2 O 3 /HfO 2 dielectrics deposition. 26−44 In either case, the main objective was to reduce the D it at the high-κ/Ge heterointerface.…”
Section: Introductionmentioning
confidence: 99%