Atomic layer deposition of hafnium oxide dielectrics on silicon and germanium substrates

McNeill, David; Bhattacharya, Sanjib; Wadsworth, H.; Ruddell, F.H.; Mitchell, S.J.N.; Armstrong, B.M.; Gamble, Harold

doi:10.1007/s10854-007-9337-y

Cited by 21 publications

(20 citation statements)

References 2 publications

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“…Similar deviation is seen for Silicon nanowires with SNAP [Heath 2008]. Atomic Layer Deposition for gate oxide formation has been shown to have spatial variability as low as σ=1% [McNeill et al 2007].…”

Section: Device Parametersupporting

confidence: 57%

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Variability in Nanoscale Fabrics

Narayanan

Leuchtenburg

Kina

et al. 2013

J. Emerg. Technol. Comput. Syst.

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Emerging nanodevice-based architectures will be impacted by parameter variation in conjunction with high defect rates. Variations in key physical parameters are caused by manufacturing imprecision as well as fundamental atomic scale randomness. In this article, the impact of parameter variation on nanoscale computing fabrics is extensively studied through a novel integrated methodology across device, circuit and architectural levels. This integrated approach enables to study in detail the impact of physical parameter variation across all fabric layers. A final contribution of the article includes novel techniques to address this impact. The variability framework, while generic, is explored extensively on the Nanoscale Application Specific Integrated Circuits (NASICs) nanowire fabric. For variation of σ = 10 in key physical parameters, the on current is found to vary by up to 3.5X. Circuit-level delay shows up to 118% deviation from nominal. Monte Carlo simulations using an architectural simulator found 67% nanoprocessor chips to operate below nominal frequencies due to variation. New built-in variation mitigation and fault-tolerance schemes, leveraging redundancy, asymmetric delay paths and biased voting schemes, were developed and evaluated to mitigate these effects. They are shown to improve performance by up to 7.5X on a nanoscale processor design with variation, and improve performance in designs relying on redundancy for defect tolerance, without variation assumed. Techniques show up to 3.8X improvement in effective-yield performance products even at a high 12% defect rate. The suite of techniques provides a design space across key system-level metrics such as performance, yield and area. . 2013. Variability in nanoscale fabrics: Bottom-up integrated analysis and mitigation.

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Section: Device Parametersupporting

confidence: 57%

“…5 Furthermore, physical parameters are expected to be uncorrelated since they would be influenced by separate process steps. For example, the gate oxide may be created using Atomic Layer Deposition (ALD) [McNeill et al 2007;Ritala and Leskela 2004]. There is no dependence of this parameter on any other process step.…”

Section: Device Parametermentioning

confidence: 99%

Variability in Nanoscale Fabrics

Narayanan

Leuchtenburg

Kina

et al. 2013

J. Emerg. Technol. Comput. Syst.

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“…This correspondence is possible because: 1) spatially correlated or "systematic" behavior is well-known for several parameters (e.g., gate oxide [20], transistor channel and gate linewidth [21]); and 2) the uniform array-based organization of these fabrics with identical devices and no arbitrary sizing or doping implies that sensor circuits designed using the same devices and circuit/logic styles can be representative of the fabric as a whole. In this sensor design, signal fall times are used to extract the extent of physical parameter variations for different spatially correlated parameters.…”

Section: Introductionmentioning

confidence: 99%

“…This implies that at the circuit level, the channel and gate diameters of all transistors along a same nanowire will be systematically affected. On the other hand, Atomic-Layer Deposition (ALD) is a process step commonly used for creating HfO 2 gate and bottom dielectric that also exhibits strong spatial correlation [20].…”

Section: Introductionmentioning

confidence: 99%

Parameter variation sensing and estimation in nanoscale fabrics

Zhang

Rahman

Narayanan

et al. 2014

Journal of Parallel and Distributed Computing

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“…For Si-based devices, the main focus has been on HfCl 4 as Hf source, but promising results have been reported on the use of TEMAH for the growth of HfO 2 on Ge. [8][9][10][11][12] Because of the low vapor pressure of the TEMAH precursor, Ar was used as carrier gas. All experiments were carried out at a substrate temperature of 200°C.…”

mentioning

confidence: 99%

In situ synchrotron based x-ray fluorescence and scattering measurements during atomic layer deposition: Initial growth of HfO2 on Si and Ge substrates

Devloo-Casier¹,

Dendooven²,

Ludwig³

et al. 2011

Applied Physics Letters

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The initial growth of HfO 2 was studied by means of synchrotron based in situ x-ray fluorescence ͑XRF͒ and grazing incidence small angle x-ray scattering ͑GISAXS͒. HfO 2 was deposited by atomic layer deposition ͑ALD͒ using tetrakis͑ethylmethylamino͒hafnium and H 2 O on both oxidized and H-terminated Si and Ge surfaces. XRF quantifies the amount of deposited material during each ALD cycle and shows an inhibition period on H-terminated substrates. No inhibition period is observed on oxidized substrates. The evolution of film roughness was monitored using GISAXS. A correlation is found between the inhibition period and the onset of surface roughness.

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Atomic layer deposition of hafnium oxide dielectrics on silicon and germanium substrates

Cited by 21 publications

References 2 publications

Variability in Nanoscale Fabrics

Variability in Nanoscale Fabrics

Parameter variation sensing and estimation in nanoscale fabrics

In situ synchrotron based x-ray fluorescence and scattering measurements during atomic layer deposition: Initial growth of HfO2 on Si and Ge substrates

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