Atomic Layer Deposition of High k Dielectric and Metal Gate Stacks for MOS Devices

Senzaki, Yoshihide; Choi, Kwang-Il; Kirsch, P. D.; Majhi, P.; Lee, Byoung Hun

doi:10.1063/1.2062940

Cited by 6 publications

(5 citation statements)

References 10 publications

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“…[2] [21] Films obtained by ALD at 500 o C also exhibit an orthorhombic phase, whereas when performed at 325 o C weak peaks of the tetragonal phase were also observed. [2] [5] [17] Cubic nano-crystallites of Hf O 2 were also observed at growth performed at 900 o C. [2] [22] [23] These characteristics are closely determined by the processing conditions under which the films are grown, complicating the formation of our gate oxide. [2] [23] Thus, it is preferable to grow perfectly amorphous or single crystalline Hf O 2 films for CM OS applications.…”

Section: Structural Propertiesmentioning

confidence: 99%

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An Investigation into the $HfO_2/Si$ Interface: Materials Science Challenges and their Effects on MOSFET Device Performance

Muralidharan¹

2022

Preprint

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Since the 1960's when Gordon Moore proposed that the transistor density in our electronic devices should double every two years while the cost is halved, the semiconductor industry has taken this statement to heart. Over the last few decades, no other industry has seen growth even comparably close to that experienced by the semiconductors industry. This has all been made possible by the unbroken string of ingenious breakthroughs by brilliant minds that have been working tirelessly to shrink down transistors. The latest of which is the use of high-k dielectrics and a return to metal gates combined with 3D-transistor architectures. This has been the enabling technology for the transition from the 90 nm node to the 45 nm node, allowing us to shrink our transistors further without losing additional gate control. The fundamental reason for using a high-k gate dielectric compared to SiO 2 is that shrinking our gate oxide further, which is already at a few angstroms, is no longer a feasible option to gain additional gate control. High-k dielectric overcome this by exploiting the fundamental physics of capacitors and the materials science of dielectrics to provide a viable option to increase gate control without the need for successively thinner gate oxides. Hafnium Oxide (Hf O 2 ) is the most studied and popular of such materials. Its high dielectric constant ∼ 16 − 25 and interface stability with silicon at operating temperatures make it an ideal candidate for use in current CM OS technology. Intel has been using Hf O 2 for their logic technology foundries for its 32 nm node and Micron its partner in memory has been using Hf O 2 for its DRAM access transistors and capacitors for the 50 nm node, all since the early 2010's. Despite its deceivingly simple appearance, the processes involved in the fabrication of such high-k Hf O 2 /Si interfaces are full of process subtleties and fabrication nuances. One of the primary reasons for this is the formation of a SiO 2 interlayer after deposition at process temperatures (∼ 600 o C −1000 o C) which degrades our final transistors gate control and ultimately the device characteristics.In this term paper we hope to explore the physics and materials science of these high-k Hf O 2 /Si interfaces, discussing the challenges and ways to overcome them when it comes to its actual fabrication, and how this ultimately affects our device performance. This paper is broadly divided into three sections where we look at the thermodynamics, reaction kinetics and atomic diffusion kinetics, after which we look at the effects of these parameters on device performance and fabrication.

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Section: Structural Propertiesmentioning

confidence: 99%

“…[2] [13] The deposition technique used for fabrication has significant consequences on the crystallographic structure, defect density, interface states and band alignment, further explored in following sections. [2] [15] [17] [23] Thermodynamic & Chemical Stability…”

Section: Structural Propertiesmentioning

confidence: 99%

An Investigation into the $HfO_2/Si$ Interface: Materials Science Challenges and their Effects on MOSFET Device Performance

Muralidharan¹

2022

Preprint

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“…The advantages of using ALD to deposit metal gate can be summarized as: excellent thin film thickness uniformity, excellent composition control (doping by inserting dopant layers), little plasma damage to gate oxide (especially for thermal ALD) compared to PVD, lower deposition temperature with low impurity compared to CVD, and conformality at nanoscale structures, especially for 3D devices [60]. Senzaki et al [59] gave the other specifications include V t stability (~±10 mV of unstressed film), Mobility ≥ 95% of that achieved with SiO 2 , density of interface traps (D it ) ≤ 5 × 10 10 cm −2 •eV, high frequency (100 kHz) CV hysteresis ≤ 10 mV, Reliability comparable to Poly-Si/SiO 2 , and thickness uniformity (3 sigma) ≤ 4%.…”

Section: Metal Gate For Finfets and Gaa-fetsmentioning

confidence: 99%

“…For GAA FETs, however, both PVD and CVD will be phased out from the deposition of gate layers, replaced by ALD. The advantages of using ALD to deposit metal gate can be summarized as: excellent thin film thickness uniformity, excellent composition control (doping by inserting dopant layers), little plasma damage to gate oxide (especially for thermal ALD) compared to PVD, lower deposition temperature with low impurity compared to CVD, and conformality at nanoscale structures, especially for 3D devices [59].…”

Section: Metal Gate For Finfets and Gaa-fetsmentioning

confidence: 99%

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Atomic Layer Deposition (ALD) of Metal Gates for CMOS

Zhao

Xiang

2019

Applied Sciences

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The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

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Enabling Processes and Integration

Silicon Devices and Process Integration

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Atomic Layer Deposition of High k Dielectric and Metal Gate Stacks for MOS Devices

Cited by 6 publications

References 10 publications

An Investigation into the $HfO_2/Si$ Interface: Materials Science Challenges and their Effects on MOSFET Device Performance

An Investigation into the $HfO_2/Si$ Interface: Materials Science Challenges and their Effects on MOSFET Device Performance

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

Enabling Processes and Integration

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