ATPG method with a hybrid compaction technique for combinational digital systems

Khatri, Abdul Rafay; Hayek, Ali; Börcsök, Josef

doi:10.1109/sai.2016.7556091

Cited by 16 publications

(9 citation statements)

References 25 publications

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“…The main advantage of fault injection at the code level is to create the state of the art methods and also develop the new methods with little effort. More details about this tool can be found in [11], [12], [13], [15], [16].…”

Section: The Rasp-fit Tool and Simulation Environmentmentioning

confidence: 99%

“…These modified designs are now used for the fault simulation/emulation, digital testing and dependability analysis, with FPGA tools, without much effort. The development of this tool is presented in previous research [11], [12], [15], [13], [16], [17], [18]. In this paper, serial fault simulation is validated for ISCAS'85 benchmark designs.…”

Section: A Rasp-fit Verilog Code Modifiermentioning

confidence: 99%

“…In previous research, Khatri et al proposed and developed a fault injection tool and named it RASP-FIT (RechnerArchitektur und SystemProgrammierung-Fault Injection Tool) tool [10], [11], [12], [13], [14], [15], [16]. This tool is used to instrument the Field Programmable Gate Array (FPGA) based designs.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

Khatri¹,

Hayek²,

Börcsök³

2020

IJACSA

Self Cite

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Fault simulation is the critical approach for many applications such as fault detection & diagnostics, test set quality measurement, generation of test vectors, circuit testability, and many others along with the help of fault injection technique. The fault simulation approach is divided into many types. The most straightforward approach among them is a serial fault simulation. In the simulation process, the circuit under test is faulted, and a faulty copy is achieved by either using a simulator command technique or instrumentation technique. A fault simulator must examine the behaviour of specified target fault in design and classified as detected or undetected by the applied test patterns. To modify the original code is a very challenging and time-consuming task. Therefore, the RASP-FIT tool is developed, which alters the fault-free FPGA design, which is under investigation, at the Verilog HDL code level. It produces the copies of faulty design along with the top design file for several fault simulation methods. Using this tool, a serial fault simulation environment can easily be created with no much effort. In this work, a serial fault simulation method is verified and validated using the RASP-FIT tool for an ISCAS'85 benchmark design as an example.

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Section: The Rasp-fit Tool and Simulation Environmentmentioning

confidence: 99%

Section: A Rasp-fit Verilog Code Modifiermentioning

confidence: 99%

See 1 more Smart Citation

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

Khatri¹,

Hayek²,

Börcsök³

2020

IJACSA

Self Cite

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show abstract

“…Test and reliability evaluation using fault injection techniques require the modification of the design. Modification of Verilog code for various FPGA-based designs and obtaining the compact test vectors for maximum fault coverage using static compaction technique, also hardness analysis provides the information about the critical nodes of design are presented in previous work [19], [1], [6]. Fig.…”

Section: A Verilog Code Modifier Under Rasp-fit Toolmentioning

confidence: 99%

Validation of the Proposed Hardness Analysis Technique for FPGA Designs to Improve Reliability and Fault-Tolerance

Khatri¹,

Hayek²,

̈ok³

2018

ijacsa

Self Cite

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Reliability and fault tolerance of FPGA systems is a major concern nowadays. The continuous increase of the system's complexity makes the reliability evaluation extremely difficult and costly. Redundancy techniques are widely used to increase the reliability of such systems. These techniques provide a large area & time overheads which cause more power consumption and delay, respectively. An experimental evaluation method is proposed to find critical nodes of the FPGA-based designs, named "hardness analysis technique" under the proposed RASP-FIT tool. After finding the critical nodes, the proposed redundant model is applied to those locations of the design and the code is modified. The modified code is functionally equivalent and is more hardened to the soft-errors. An experimental setup is developed to verify and validate the criticality of these locations found by using hardness analysis. After applying redundancy to those locations, the reliability is evaluated concerning failure rate reduction. Experimental results on ISCAS'85 combinational benchmarks show that a min-max range of failure reduction (14%-85%) is achieved compared to the circuit without redundancy under the same faulty conditions, which improves reliability.

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“…Authors have injected a total of 12 faults in the c17 benchmark circuit in different locations of the design, 4 faults in each TMR module. The way of injecting faults in the Verilog design code is described in our previous work [3], [18], [19].…”

Section: Simulation Verification Using Fault Injection Techniquementioning

confidence: 99%

RASP-TMR: An Automatic and Fast Synthesizable Verilog Code Generator Tool for the Implementation and Evaluation of TMR Approach

Khatri¹,

Hayek²,

Börcsök³

2018

ijacsa

Self Cite

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Triple Modular Redundancy (TMR) technique is one of the most well-known techniques for error masking and Single Event Effects (SEE) protection for the FPGA designs. These FPGA designs are mostly expressed in hardware description languages, such as Verilog and VHDL. The TMR technique involves triplication of the design module and adding the majority voter circuit for each output port. Building this triplication scheme is a non-trivial task and requires a lot of time and effort to alter the code of the design. In this paper, the RASP-TMR tool is developed and presented that has functionalities to take a synthesizable Verilog design file as an input, parse the design and triplicate it. The tool also generates a top-level module in which all three modules are instantiated and finally adds the proposed majority voter circuit. This tool, with its graphical user interface, is implemented in MATLAB. The tool is simple, fast and user-friendly. The tool generates the synthesizable design that facilitates the user to evaluate and verify the TMR design for FPGA-based systems. A simulation scenario is created using Xilinx ISE tools and ISim simulator. Different fault models are examined during simulations such as bit-flip and stuck at 1/0. The results using various benchmark designs demonstrate that the tool produces synthesizable code and the proposed majority voter logic perfectly masks the error/failure.

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ATPG method with a hybrid compaction technique for combinational digital systems

Cited by 16 publications

References 25 publications

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

Validation of the Proposed Hardness Analysis Technique for FPGA Designs to Improve Reliability and Fault-Tolerance

RASP-TMR: An Automatic and Fast Synthesizable Verilog Code Generator Tool for the Implementation and Evaluation of TMR Approach

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