Attacking the one-out-of-m multicore problem by combining hardware management with mixed-criticality provisioning

Kim, Namhoon; Ward, Bryan C.; Chisholm, Micaiah; Anderson, James H.; Smith, F. Donelson

doi:10.1007/s11241-017-9272-9

Cited by 34 publications

(14 citation statements)

References 30 publications

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“…Our measurements for several benchmark programs on our Cortex A9 platform exhibit similar behavior [12]. We note three properties that directly follow from this assumption.…”

Section: Linear Programmingsupporting

confidence: 54%

“…In a companion paper [12], we describe how these features were implemented and present experiments that demonstrate the virtues of the supported isolation mechanisms in MC systems. In that effort, we considered a single generic LLC allocation strategy.…”

Section: MCmentioning

confidence: 99%

“…To analyze the effectiveness of this approach, we present a schedulability study involving randomly generated task systems where generated task execution times were based on measurement data. In this study, the usage of our techniques enabled schedulability improvements of up to 100% for some task-system categories in comparison to two generic task-system-oblivious LLC allocation strategies, including that considered in [12]. The presented LP can be solved as either an ordinary LP or a mixed-integer LP (MILP).…”

Section: MCmentioning

confidence: 99%

See 2 more Smart Citations

Cache Sharing and Isolation Tradeoffs in Multicore Mixed-Criticality Systems

Chisholm

Ward

Kim

et al. 2015

2015 IEEE Real-Time Systems Symposium

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In mixed-critical applications, tension exists between sharing and isolation with respect to hardware resources: while strong isolation might be required for highly critical tasks, somewhat permissive sharing might be reasonable for less critical tasks to improve throughput or average-case performance. In this paper, this tension is examined as it pertains to shared last-level caches (LLCs) on multicore platforms. In particular, criticality-aware optimization techniques based on linear programming are presented for allocating LLC areas in the context of the previously proposed MC 2 (mixed-criticality on multicore) framework. Experiments are also presented that show that these techniques can result in significant schedulability improvements.

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“…Our measurements for several benchmark programs on our Cortex A9 platform exhibit similar behavior [12]. We note three properties that directly follow from this assumption.…”

Section: Linear Programmingsupporting

confidence: 54%

Section: MCmentioning

confidence: 99%

Section: MCmentioning

confidence: 99%

See 1 more Smart Citation

Cache Sharing and Isolation Tradeoffs in Multicore Mixed-Criticality Systems

Chisholm

Ward

Kim

et al. 2015

2015 IEEE Real-Time Systems Symposium

Self Cite

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“…Previous work has also explored hardware-based approaches to dynamically allocate cache partitions to tasks, e.g., using the PL310 cache controller [27] or the Intel's CAT [32]. Some techniques also combine software and hardware approaches to support finer-granularity partitions [8,16]. However, these techniques cannot be directly applied to virtualization platforms.…”

Section: Related Workmentioning

confidence: 99%

“…We reserved cache partitions 0-7 (CBM bitmask 0×000FF) to CPU1 and partitions 8-15 (CBM bitmask 0×0FF00) to CPU2. We flushed the entire cache initially, and mitigated potential interference to CPU1 and CPU2 by moving all system services to the remaining cores and assigning to them the remaining partitions (partitions [16][17][18][19]. We created a periodic task that sequentially accesses a 4MB array.…”

Section: Cache Lookup Controlmentioning

confidence: 99%

vCAT: Dynamic Cache Management Using CAT Virtualization

Thi²,

Phan

et al. 2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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This paper presents vCAT, a novel design for dynamic shared cache management on multicore virtualization platforms based on Intel's Cache Allocation Technology (CAT). Our design achieves strong isolation at both task and VM levels through cache partition virtualization, which works in a similar way as memory virtualization, but has challenges that are unique to cache and CAT. To demonstrate the feasibility and benefits of our design, we provide a prototype implementation of vCAT, and we present an extensive set of microbenchmarks and performance evaluation results on the PARSEC benchmarks and synthetic workloads, for both static and dynamic allocations. The evaluation results show that (i) vCAT can be implemented with minimal overhead, (ii) it can be used to mitigate shared cache interference, which could have caused task WCET increased by up to 7.2 x, (iii) static management in vCAT can increase system utilization by up to 7 x compared to a system without cache management; and (iv) dynamic management substantially outperforms static management in terms of schedulable utilization (increase by up to 3 x in our multi-mode example use case). Abstract-This paper presents vCAT, a novel design for dynamic shared cache management on multicore virtualization platforms based on Intel's Cache Allocation Technology (CAT). Our design achieves strong isolation at both task and VM levels through cache partition virtualization, which works in a similar way as memory virtualization, but has challenges that are unique to cache and CAT. To demonstrate the feasibility and benefits of our design, we provide a prototype implementation of vCAT, and we present an extensive set of microbenchmarks and performance evaluation results on the PARSEC benchmarks and synthetic workloads, for both static and dynamic allocations. The evaluation results show that (i) vCAT can be implemented with minimal overhead, (ii) it can be used to mitigate shared cache interference, which could have caused task WCET increased by up to 7.2×, (iii) static management in vCAT can increase system utilization by up to 7× compared to a system without cache management; and (iv) dynamic management substantially outperforms static management in terms of schedulable utilization (increase by up to 3× in our multi-mode example use case). Disciplines Computer Engineering | Computer Sciences

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