Attacking the One-Out-Of-m Multicore Problem by Combining Hardware Management with Mixed-Criticality Provisioning

Abstract

The multicore revolution is having limited impact in safety-critical application domains. A key reason is the "one-out-of-m" problem: when validating real-time constraints on an m-core platform, excessive analysis pessimism can effectively negate the processing capacity of the additional m − 1 cores so that only "one core's worth" of capacity is available. Two approaches have been investigated previously to address this problem: mixed-criticality allocation techniques, which provision less-critical software components less pessimistically, and hardware-management techniques, which make the underlying platform itself more predictable. A better way forward may be to combine both approaches, but to show this, fundamentally new criticality-cognizant hardwaremanagement tradeoffs must be explored. Such tradeoffs are investigated herein in the context of a large-scale, overheadaware schedulability study. This study was guided by extensive trace data obtained by executing benchmark tasks on a new variant of the MC 2 framework that supports configurable criticality-based hardware management. This study shows that the two approaches mentioned above can be much more effective when applied together instead of alone.978-1-4673-8641-8/16/$31.00

RT-Gang: Real-Time Gang Scheduling Framework for Safety-Critical Systems

“…When a task's WCET has to be assumed 10X or 100X its solo execution time, we can see why in aviation industry, it makes perfect sense to disable all but one core [25] and why the certification authorities in US and Europe recommend it for certification [11], [12]. However, disabling cores obviously defeats the purpose of using multicore platforms in the first place-the need of more performance.…”

“…Some COTS processors [22], [33] support cache-way partitioning [49]. Mancuso et al [33] and Kim et al [25], used both coloring and cache way partitioning for fine-grained cache partitioning. While these shared resource partitioning techniques can reduce space conflicts of some shared resources, hence beneficial for predictability, but they are not enough to guarantee strong time predictability on COTS multicore platforms because there are too many hardware resources (e.g., cache MSHRs, DRAM controller buffers, etc.)…”

Accurate ILP-Based Contention Modeling on Statically Scheduled Multicore Systems

“…Authors in [29] focus on DRAM and memory controller operations to bound the delay potentially suffered on memory accesses and propose bank partitioning as a way to reduce the amount of inter-core interference. The work in [30] combines hardware management and mixed-criticality based resource provisioning as a means to trade off isolation and sharing of resources and make multicore execution more predictable (i.e., performance guarantees for high-criticality tasks). When hardware isolation is not an option, contention can be controlled at the software level by exploiting specific RTOS support to enforce analysis-time utilization bounds.…”

Timely Fine-Grained Interference-Sensitive Run-Time Adaptation of Time-Triggered Schedules

“…The constant growth of processing demand, combined with the heat dissipation issues of single-core platforms, has led to platforms consisting of several cores that concurrently execute a high number of applications. However, the use of such multi-/many-core platforms in time-critical systems poses several challenges, such as timing interference, timing composability and the "one-out-of-m-cores" problem [1], [2].…”

“…all accesses of a task to a shared resource are assumed to conflict with all other cores, and it is valid for any task scheduling and allocation, or ii) the task scheduling and allocation is known providing essential information that allows more accurate estimation of interferences, but this WCET estimation is valid only for the given task scheduling and allocation solution. In the first case, the pessimism introduced in the WCET estimation (by being unaware of the task scheduling and allocation solution) can potentially negate the performance benefit coming from the parallel execution of the tasks on multi-cores [1] or even make the problem infeasible, if the system becomes unschedulable. In the second case, the known task scheduling and allocation solution is used to compute interference-sensitive WCET (isWCET), which are lower than the pessimistic WCET of the first case [3], [4], [5].…”