The quest to find a replacement for the traditional dielectric used in the semiconductor industry, namely, SiO 2 , is attracting an increasing amount of research. As demands for faster and less power consuming electronic devices continue to increase, device dimensions and supply voltages together with a number of other parameters are forced to lower values. In not more than 15 years the equivalent gate dielectric thickness is predicted to be as low as 10 Å. 1 If such extremely thin gate dielectrics were to consist solely of SiO 2 , the leakage current through the gate would be intolerable. 1 The main objective of research in this area is therefore to find a way to maintain or increase control of the inversion channel from the gate with decreasing voltages without increasing the leakage current through the gate dielectric. A possible solution is to replace part of the SiO 2 with a dielectric with higher permittivity thus increasing the capacitance while maintaining the superior Si-SiO 2 interface. The perhaps most commonly used combination is that with Si 3 N 4 , 2,3 but other materials, e.g., Ta 2 O 5 , 4,5 have been suggested. Another issue in gate-stack scaling is the problem with depletion of the polysilicon reducing the effective capacitance. 6 A replacement for the polysilicon will therefore probably be needed. 1 This may force the use of different gate materials for PMOS and NMOS transistors to realize satisfactory threshold voltages. For NMOS transistors, aluminum is a suitable candidate with its Fermi level close to the conduction band in the silicon. In this study the focus is on MOS structures where the gate material is aluminum. We report on a way to increase the gate-tochannel capacitance without increasing the leakage current which is possible in this particular device structure.Experimental Devices.-The devices used in this study were based on <100> oriented, 1-10 ⍀ cm substrates of n-and p-type silicon. The wafers were oxidized to form a thick field oxide followed by a lithography step where the devices with areas ranging from 2 ϫ 2 m to 100 ϫ 100 m were defined. The gate dielectric was then formed using one of the methods described below, immediately after which aluminum was evaporated from a resistively heated crucible to form the top contacts of the metal oxide semiconductor (MOS) structures. For comparison, polysilicon (POCl 3 -doped) or chromium was used as the gate material on a few devices. Finally aluminum was evaporated onto the back of the wafers.Four types of ultrathin gate dielectrics were studied, as summarized in Table I: (i) thermally grown in a 2% O 2 in N 2 mixture at 900ЊC for 20 min (denoted HTn/p); (ii) thermally grown at 750ЊC for 10 min in a pure O 2 environment (denoted LTn), (iii) deposited at 300ЊC using remote plasma-enhanced chemical vapor deposition (denoted RPECVD), and (iv) oxidized at 300ЊC using a remote oxygen plasma (denoted RPEO). For comparison, thicker oxides were grown on p-type substrates in pure oxygen at 850ЊC to a final thickness ranging from 92 to 175 Å (d...