Automated and Scalable Verification of Integer Multipliers

Abstract

The automatic formal verification of multiplier designs has been pursued since the introduction of BDDs. We present a new rewriterbased method for efficient and automatic verification of signed and unsigned integer multiplier designs. We have proved the soundness of this method using the ACL2 theorem prover, and we can verify integer multiplier designs with various architectures automatically, including Wallace, Dadda, and 4-to-2 compressor trees, designed with Booth encoding and various types of final stage adders. Our experiments have shown that our approach scales well in terms of time and memory. With our method, we can confirm the correctness of 1024 × 1024-bit multiplier designs within minutes.

RP-Rewriter: An Optimized Rewriter for Large Terms in ACL2

“…For this specific problem, users might derive various solutions; for example, it is possible to prove a lemma that terms of this form satisfy evenp, or alternatively we can set neg-m2 as an invisible function for + for the loop-stopper algorithm (this keeps a and neg-m2 next to each other) and prove some simple lemmas to show evenness. However, for cases where terms are very large and the arguments are rewritten to different terms, which is the case for our multiplier design proofs [3], then neither of these solutions would work. In fact for our multiplier proofs, we have not been able to find a feasible solution using the built-in rewriter, other than possibly creating a complex meta rule to show evenness, which would likely be very tedious to implement and costly for proof-time performance.…”

“…We use RP-rewriter to implement our verification method for multiplier designs, which is based completely on term rewriting [3]. We make extensive use of performance benefits of side-conditions and fast-alist support.…”

Balancing Automation and Control for Formal Verification of Microprocessors

“…Besides interfaces to trusted tools, ACL2 has a mechanism for extending its reasoning by admitting verified clause-processors [2]. We use this feature in several ways, notably for SVL [43], a routine that automates verification of multipliers, and for FGL, the core tool that provides automation for our microoperation execution and microcode proofs.…”

Verified Implementation of an Efficient Term-Rewriting Algorithm for Multiplier Verification on ACL2

“…We have created a new term-rewriting algorithm that can efficiently and automatically verify large arithmetic circuit designs with embedded multipliers [29,30]. We have shown that this algorithm can verify designs with millions of gates in just a few minutes.…”

“…Additionally, terms might change so drastically during rewriting that it might become too difficult to apply some rewrite rules. In our previous work, we have described only the term-rewriting algorithm itself [29,30], and some features of the supporting rewriter technology [27]. The goal of this paper is to elaborate on the multiplier-specific implementation details and notable challenges.…”