Automated correction of design errors by edge redirection on High-Level Decision Diagrams

Karputkin, Anton; Ubar, Raimund; Tombak, Mati; Raik, Jaan

doi:10.1109/isqed.2012.6187566

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Classic Application Of Formal Methods In Hardware Verification1

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2013

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“…This fact resulted in techniques like Predicate Abstraction as used in [17,3], or Term-Level Abstraction as practiced in [21]. In [19], High-Level Decision Diagrams (HLDDs) have been not only used to describe a system's behavior but also to correct wrong transitions automatically.…”

Section: Classic Application Of Formal Methods In Hardware Verificationmentioning

confidence: 99%

Automatized high-level evaluation of security properties for RTL hardware designs

Höller

Preschern

Steger

et al. 2013

Proceedings of the Workshop on Embedded Systems Security

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The ever increasing integration of embedded systems into our every lives created a strong demand for trustable software and hardware implementations. To provide such trust between manufacturer and customer of integrated systems, regulatory rules like the Common Criteria have been defined. While this international standard clearly prescribes the usage of formal methods at high assurance level, formal verification at code-level is not widespread in practice. This work introduces a novel approach to verify the correct functionality of security critical hardware implementations under fault conditions. Generality is enabled by high-level evaluation using state machines extracted in an automatized way.

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Section: Classic Application Of Formal Methods In Hardware Verificationmentioning

confidence: 99%

Automatized high-level evaluation of security properties for RTL hardware designs

Höller

Preschern

Steger

et al. 2013

Proceedings of the Workshop on Embedded Systems Security

View full text Add to dashboard Cite

show abstract

Automated correction of design errors by edge redirection on High-Level Decision Diagrams

Cited by 1 publication

References 11 publications

Automatized high-level evaluation of security properties for RTL hardware designs

Automatized high-level evaluation of security properties for RTL hardware designs

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