Automated data cache placement for embedded VLIW ASIPs

Abstract

Memory bandwidth issues present a formidable bottleneck to accelerating embedded applications, particularly data bandwidth for multiple-issue VLIW processors. Providing an efficient ASIP data cache solution requires that the cache design be tailored to the target application. Multiple caches or caches with multiple ports allow simultaneous parallel access to data, alleviating the bandwidth problem if data is placed effectively. We present a solution that greatly simplifies the creation of targeted caches and automates the process of explicitly allocating individual memory access to caches and banks. The effectiveness of our solution is demonstrated with experimental results.

Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems

“…The design space is explored with the goal to optimize hardware cost, code size, and performance. The analysis involves only the microprocessor without considering the memory subsystem, which has been proved to be fundamental to meet the overall performance and power design constraints [Hennessy and Patterson 2006;Venkatachalam and Franz 2005;Balasubramonian et al 2000], especially in a VLIW scenario [Raghavan et al 2006;Morgan et al 2005;Abraham and Mahlke 1999]. Although the approach is interesting, it is not general, but depends on the system architecture being considered.…”

Cache miss reduction through hardware-assisted loop optimization

“…The research on the cache miss reduction via ASIP is still in its infancy, which usually uses the features of its configurable architecture to achieve the objectives. For example, an automated allocation algorithm and software are presented to guide the cache configuration for ASIPs [10]. However, this algorithm only considers the data cache without instruction cache.…”