Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Papameletis, Christos; Keller, B.; Chickermane, V.; Marinissen, Erik Jan; Hamdioui, Said

doi:10.1109/ets.2013.6569350

Cited by 12 publications

(5 citation statements)

References 18 publications

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“…To support the test of multi-tower 3D-SIC, a generic DFT architecture based on die-level wrappers for 3D-SICs with any numbers of "towers" has been proposed in [2]. Similarly, Papameletis et al extend existing 3D-DFT architecture with support for wrapped embedded IP cores and multiple tower stacks [3]. On the aspect of test scheduling, Noia et al introduce optimization methods for minimizing the test time for the final stack test [4].…”

Section: Introductionmentioning

confidence: 98%

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QPSO based test scheduling for 3D-SIC with multiple towers

Wang

Xue

2016

2016 China Semiconductor Technology International Conference (CSTIC)

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3D-SIC with multiple towers, which integrates multiple stacked die-towers on the bottom die, enhances the performance and integration density of semiconductor chips. Test scheduling helps to reduce test time of the complex chips. Towards the whole integration process of 3D-SICs, Quantum-behaved Particle Swarm Optimization (QPSO) based test scheduling algorithm is proposed. Experimental results show that the algorithm can reduce total test time of 3D-SIC significantly, and the test time is affected by the number of test pins and test Through-Silicon Vias (TSVs). It is found out that the 3D-SIC with the complex dies as the top dies result in shorter test time.

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Section: Introductionmentioning

confidence: 98%

“…a). Though test architecture for multi-tower 3D-SIC is proposed in [2][3], they offer no insight into test scheduling. Towards these issues, this work tries to apply QPSO algorithm to address the problem of test scheduling for 3D-SIC with multiple towers, either for final stack test or for any number of partial stacks during bonding.…”

Section: Introductionmentioning

confidence: 99%

QPSO based test scheduling for 3D-SIC with multiple towers

Wang

Xue

2016

2016 China Semiconductor Technology International Conference (CSTIC)

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“…3D test architecture include Design-for-test (DfTs) solutions for post-bond test providing modular test access to all components through the stacked tiers [2]. Also, the on-going development on 3D test standards suggest insertion of wrapped embedded cores [3] and dedicated scan flip-flops between TSVs [4].…”

Section: Introductionmentioning

confidence: 99%

TSV aware timing analysis and diagnosis in paths with multiple TSVs

Metzler

Todri‐Sanial

Bosio

et al. 2014

2014 IEEE 32nd VLSI Test Symposium (VTS)

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3D-IC test becomes a challenge with the increasing number of TSVs and demands for effective 3D aware test techniques. In this work, we propose a timing aware model to capture delay variations on a path due to resistive open TSVs. The key idea is to analytically model delay and apply our correlation-based resistive open TSV detection method to attain path delay fault coverage. We propose two methods to investigate timing variation introduced by resistive open TSVs in a critical path delay with multiple TSVs. Method I computes the correlation of multiple TSVs in a path to overall path delay to determine if TSVs are the source of the introduced delay. Method II pinpoints which TSV is faulty by computing the delay fault coverage of each TSV in a path with multiple TSVs. Our results indicate the accuracy of our proposed method and promotes early identification of resistive open defects TSVs.

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“…INTRODUCTION Tremendous effort has been put in place to bring throughsilicon via (TSV) based 2.5D and 3D-SIC technology closer to market [1][2][3]. Realizing such ICs is attractive due to major benefits [4] such as (a) increased electrical performance, (b) reduced power consumption due to shortened interconnects, (c) heterogeneous integration, (d) reduced form factor, etc.…”

mentioning

confidence: 99%

Quality versus cost analysis for 3D Stacked ICs

Taouil

Hamdioui

Marinissen

2014

2014 IEEE 32nd VLSI Test Symposium (VTS)

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To fulfill customer demands, IC products must satisfy the required quality generally expressed in defective parts per million (DPPM). To meet this DPPM target, appropriate test infrastructures and test approaches must be developed. This is a challenging task for 3D Stacked-ICs (3D-SIC) due to a large test flow space; each test flow may require different design-fortest features and impact the product quality and total stack cost differently. Therefore, appropriate models to predict the impact of test flows on the product quality and overall stack cost at early design stage is important for quality versus cost trade-offs. This paper presents a model that predicts the 3D product quality in terms of DPPM for different test flows and associated cost; it incorporates the quality of the wafer manufacturing, stacking and packaging process. For example, the presented case study showed that maintaining the same product quality for larger stack size might result in a significant test cost increase.

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Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers

Cited by 12 publications

References 18 publications

QPSO based test scheduling for 3D-SIC with multiple towers

QPSO based test scheduling for 3D-SIC with multiple towers

TSV aware timing analysis and diagnosis in paths with multiple TSVs

Quality versus cost analysis for 3D Stacked ICs

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