Automated Framework for General-Purpose Genetic Algorithms in FPGAs

Guo, Liucheng; Thomas, David B.; Luk, Wayne

doi:10.1007/978-3-662-45523-4_58

Cited by 4 publications

(1 citation statement)

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“…Therefore, the population needs to be kept in a single memory that is accessed by the processing units that compute the operations of the algorithm. One approach is to generate a new population at each iteration of the algorithm (generational GA), where it is possible to have several parallel units that access to the population and generate new solutions [6], [7]. Nevertheless, the access to the memory that keeps the population may represent an important bottleneck when the level of parallelism increases.…”

Section: Introductionmentioning

confidence: 99%

An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem

Santos

Alves

Ferreira

2015

2015 Euromicro Conference on Digital System Design

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Solving complex optimization problems with genetic algorithms (GAs) with custom computing architectures is a way to improve the execution time of this metaheuristic, which is known to consume considerable amounts of time to converge to final solutions. In this work, we present a scalable computing array architecture to accelerate the execution of cellular GAs (cGAs), a variant of genetic algorithms which can conveniently exploit the coarse-grain parallelism afforded by custom parallel processing. The proposed architecture targets Xilinx FPGAs and is used as an auxiliary processor of an embedded CPU (MicroBlaze). To handle different optimization problems, a high-level synthesis (HLS) design flow is proposed where the problem-dependent operations are specified in C++ and synthesised to custom hardware, thus requiring a minimum knowledge of digital design for FPGAs. The minimum energy broadcast (MEB) problem in wireless ad hoc networks is used as a case study. An existing software implementation of a GA to solve this problem is ported to the proposed computing array to demonstrate its effectiveness and the HLS-based design flow. Implementation results in a Virtex-6 FPGA show significant speedups, while finding solutions with improved quality.

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Section: Introductionmentioning

confidence: 99%