Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, Kimiyoshi; Nogami, K.; Igarashi, M.; Minami, Fumihiro; Kawasaki, Yukio; Ishikawa, Takashi; Kanazawa, M.; Aoki, Takahiro; Takano, M.; Mizuno, C.; Ichida, M.; Sonoda, S.; Takahashi, Masafumi; Hatanaka, N.

doi:10.1109/cicc.1997.606600

Cited by 115 publications

(152 citation statements)

References 7 publications

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“…Level conversion (if necessary) is done in the flip flops at the end of the circuit paths. An extension to this approach is proposed in [7], which is based on the observation that by optimizing the insertion points of level converters, one can increase the number of gates using V DD,L without increasing the number of level converters. This leads to higher power savings.…”

Section: Multiple-voltage Designmentioning

confidence: 99%

Low-power RT-level synthesis techniques: a tutorial

Pedram

Abdollahi

2005

IEE Proc., Comput. Digit. Tech.

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-Power consumption and power-related issues have become a first-order concern for most designs and loom as fundamental barriers for many others. And, while the primary method used to date for reducing power has been supply voltage reduction, this technique begins to lose its effectiveness as voltages drop to sub-one volt range and further reductions in the supply voltage begin to create more problems than are solved. Under these circumstances, the process of design and the automation tools required to support that process become the critical success factors. In the last decade, huge effort has been invested to come up with a wide range of design solutions that help solve the power dissipation problem for different types of electronic devices, components and systems. These techniques range from RTL power management and multiple voltage assignment, to power-aware logic synthesis and physical design, to memory and bus interface design. This tutorial paper explains a number of representative low power design techniques from this large set. More precisely, we will describe basic techniques, applicable at RT-level and below, that have proven to hold good potential for power optimization in practical design environments.

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Section: Multiple-voltage Designmentioning

confidence: 99%

Low-power RT-level synthesis techniques: a tutorial

Pedram

Abdollahi

2005

IEE Proc., Comput. Digit. Tech.

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“…Clustered voltage scaling (CVS) [18] and extended clustered voltage scaling (ECVS) [19] algorithms are two main heuristic methods of assigning dual supply voltages to gates in a circuit. CVS assigns V DDL to gates with positive time slack starting from primary outputs to primary inputs and so dose not allow the V DDL gates to feed directly into V DDH gates by grouping gates into V DDH and V DDL clusters.…”

Section: Dual Voltage Design and Level Converters In Subthresholdmentioning

confidence: 99%

“…Utilizing the time slack for dual V dd is a well-known technique for a circuit operating with nominal V dd for reducing the power consumption with small extra cost in physical design [18], [19]. However, operation in the subthreshold voltage region has been long predicted and since verified [20].…”

Section: Introductionmentioning

confidence: 99%

Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates

Kim

Agrawal

2011

2011 12th International Symposium on Quality Electronic Design

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Abstract-This paper presents a method for minimum energy digital CMOS circuit design using dual subthreshold supply voltages. Stringent energy budget and moderate speed requirements of some ultra low power systems may not be best satisfied just by scaling a single supply voltage. Optimized circuits with dual supply voltages provide an opportunity to resolve these demands. The delay penalty of a traditional level converter is unacceptably high when the voltages are in the subthreshold range. In the present work level converters are not used and special multiple logic-level gates are used only when, after accounting for their cost, they offer advantage. Starting from a lowest per cycle energy design whose single supply voltage is in the subthreshold range, a new mixed integer linear program (MILP) finds a second lower supply voltage optimally assigned to gates with time slack. The MILP accounts for the energy and delay characteristics of logic gates interfacing two different signal levels. New types of linearized AND and OR constraints are used in this MILP. We show energy saving up to 24.5% over the best available designs of ISCAS'85 benchmark circuits.

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“…Fig. 2(a) shows the traditional level shifter, called Dual Cascode Voltage Switch (DCVS), which has been used in [2,3,5,6]. Simulation results show that the power consumption of this level shifter is about four to five times that of an inverter.…”

Section: A Level Shiftermentioning

confidence: 99%

“…Since the LS circuit consumes power and has a considerable delay, minimizing the number of level-shifters is important in the voltage scaling technique. Considering this fact, a few techniques have been proposed to deal with voltage scaling at the gate level [3][4][5][6]. The most popular of them is Cluster Voltage Scaling (CVS) [5], in which the level shifters are used just in the front of the primary outputs.…”

Section: Introductionmentioning

confidence: 99%

Enhancing the Efficiency of Cluster Voltage Scaling Technique for Low-power Application

Amelifard

Afzali-Kusha

Khadernzadeh

2005 IEEE International Symposium on Circuits and Systems

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Abstract-In this paper, a scheme for power reduction based on Cluster Voltage Scaling (CVS) for gate-level design of the VLSI circuits is presented. To increase the power reduction efficiency of the previous CVS techniques, a new low power level-shifter is utilized in the circuit. In addition, the concept of transistor ordering has been used to further reduce the power consumption. This technique shows an average improvement of 7% compared to the previous CVS circuits. The impact of CVS and its modified version on the reduction of short-circuit and leakage power are also discussed.

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Automated low-power technique exploiting multiple supply voltages applied to a media processor

Cited by 115 publications

References 7 publications

Low-power RT-level synthesis techniques: a tutorial

Low-power RT-level synthesis techniques: a tutorial

Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates

Enhancing the Efficiency of Cluster Voltage Scaling Technique for Low-power Application

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