2020
DOI: 10.1109/tcad.2018.2889665
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Automated Nonintrusive Analysis of Electronic System Level Designs

Abstract: Due to the ever increasing complexity of hardware systems, designers strive for higher levels of abstractions in the early stages of the design process. Modeling hardware at the electronic system level (ESL) is one way to address this demand, with the C++-based system modeling framework SystemC and its abstract communication library transaction level modeling (TLM) having become de-facto standards for ESL system design. While the C++ compiler is sufficient to compile and simulate a given ESL design, for tasks … Show more

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Cited by 18 publications
(1 citation statement)
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“…Since the cost of ixing any security laws (e.g., information low policies) increases with the stage of development, the validation process should be performed as early as possible [14]. For the early design entry, Virtual Prototype (VP) [11,15,20] is being increasingly adopted by the semiconductor industry. A VP is an abstract and executable software model that is typically implemented using SystemC [6,18,26] and its Transaction Level Modeling (TLM) [2] framework at the Electronic System Level (ESL) [10,33].…”
Section: Introductionmentioning
confidence: 99%
“…Since the cost of ixing any security laws (e.g., information low policies) increases with the stage of development, the validation process should be performed as early as possible [14]. For the early design entry, Virtual Prototype (VP) [11,15,20] is being increasingly adopted by the semiconductor industry. A VP is an abstract and executable software model that is typically implemented using SystemC [6,18,26] and its Transaction Level Modeling (TLM) [2] framework at the Electronic System Level (ESL) [10,33].…”
Section: Introductionmentioning
confidence: 99%