Automated OS-level Device Runtime Power Management

Xu, Chao; Lin, Felix Xiaozhu; Wang, Yuyang; Lin, Zhouchen

doi:10.1145/2694344.2694360

Cited by 21 publications

(10 citation statements)

References 21 publications

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“…Closer to our goal of platform power management, for modern servers and phones it is usually the OS's responsibility to implement power management policies -deciding which components to power on or turn off is important to minimize the power requirements. Xu et al argue for a centralized power management agent [46,47] which decides when devices should switch between the discrete enabled or disabled states based on quality-of-service (QoS) requirements and specification of power states. QoS can also be used by agents in embedded systems to automatically find appropriate dynamic power states [16].…”

Section: Related Workmentioning

confidence: 99%

Declarative Power Sequencing

Schult

Schwyn

Giardino

et al. 2021

ACM Trans. Embed. Comput. Syst.

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Modern computer server systems are increasingly managed at a low level by baseboard management controllers (BMCs). BMCs are processors with access to the most critical parts of the platform, below the level of OS or hypervisor, including control over power delivery to every system component. Buggy or poorly designed BMC software not only poses a security threat to a machine, it can permanently render the hardware inoperative. Despite this, there is little published work on how to rigorously engineer the power management functionality of BMCs so as to prevent this happening. This article takes a first step toward putting BMC software on a sound footing by specifying the hardware environment and the constraints necessary for safe and correct operation. This is best accomplished through automation: correct-by-construction power control sequences can be efficiently generated from a simple, trustworthy model of the platform’s power tree that incorporates the sequencing requirements and safe voltage ranges of all components. We present both a modeling language for complex power-delivery networks and a tool to automatically generate safe, efficient power sequences for complex modern platforms. This not only increases the trustworthiness of a hitherto opaque yet critical element of platform firmware: regulator and chip power models are significantly simpler to produce than hand-written power sequences. This, combined with model reuse for common components, reduces both time and cost associated with platform bring-up for new hardware. We evaluate our tool using a new high-performance 2-socket server platform with >100W per socket TDP, tight voltage limits and 25 distinct power regulators needing configuration, showing both fast (<10s) tool runtime, and correct power sequencing of a live system.

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Section: Related Workmentioning

confidence: 99%

Declarative Power Sequencing

Schult

Schwyn

Giardino

et al. 2021

ACM Trans. Embed. Comput. Syst.

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“…Improving energy efficiency in systems and applications has been thoroughly studied in the past. For example, previous works describe user-level [71,80,86,87,95,96] and kernel [75] facilities that both manage and predict power consumption. Prior works propose trading performance and/or precision for energy.…”

Section: Energy Efficiencymentioning

confidence: 99%

Lock–Unlock

Guerraoui

Guiroux

Lachaize

et al. 2018

ACM Trans. Comput. Syst.

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A plethora of optimized mutex lock algorithms have been designed over the past 25 years to mitigate performance bottlenecks related to critical sections and locks. Unfortunately, there is currently no broad study of the behavior of these optimized lock algorithms on realistic applications that consider different performance metrics, such as energy efficiency and tail latency. In this article, we perform a thorough and practical analysis of synchronization, with the goal of providing software developers with enough information to design fast, scalable, and energy-efficient synchronization in their systems. First, we perform a performance study of 28 state-of-the-art mutex lock algorithms, on 40 applications, on four different multicore machines. We consider not only throughput (traditionally the main performance metric) but also energy efficiency and tail latency, which are becoming increasingly important. Second, we present an in-depth analysis in which we summarize our findings for all the studied applications. In particular, we describe nine different lock-related performance bottlenecks, and we propose six guidelines helping software developers with their choice of a lock algorithm according to the different lock properties and the application characteristics. From our detailed analysis, we make several observations regarding locking algorithms and application behaviors, several of which have not been previously discovered: (i) applications stress not only the lock–unlock interface but also the full locking API (e.g., trylocks, condition variables); (ii) the memory footprint of a lock can directly affect the application performance; (iii) for many applications, the interaction between locks and scheduling is an important application performance factor; (vi) lock tail latencies may or may not affect application tail latency; (v) no single lock is systematically the best; (vi) choosing the best lock is difficult; and (vii) energy efficiency and throughput go hand in hand in the context of lock algorithms. These findings highlight that locking involves more considerations than the simple lock/unlock interface and call for further research on designing low-memory footprint adaptive locks that fully and efficiently support the full lock interface, and consider all performance metrics.

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“…Online approaches are applicable to applications where inputs and use-conditions are unpredictable. Related system techniques include device driver control [66,32], device interface design [9] and run-time system configuration [25]. Offline power optimization is used for predictable application tasks.…”

Section: Related Workmentioning

confidence: 99%

3DGates

Ajay

Song

Rathore

et al. 2017

SIGARCH Comput. Archit. News

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As the next-generation manufacturing driven force, 3D printing technology is having a transformative effect on various industrial domains and has been widely applied in a broad spectrum of applications. It also progresses towards other versatile fields with portable battery-powered 3D printers working on a limited energy budget. While reducing manufacturing energy is an essential challenge in industrial sustainability and national economics, this growing trend motivates us to explore the energy consumption of the 3D printer for the purpose of energy efficiency. To this end, we perform an in-depth analysis of energy consumption in commercial, off-the-shelf 3D printers from an instruction-level perspective. We build an instruction-level energy model and an energy profiler to analyze the energy cost during the fabrication process. From the insights obtained by the energy profiler, we propose and implement a cross-layer energy optimization solution, called 3DGates, which spans the instruction-set, the compiler and the firmware. We evaluate 3DGates over 338 benchmarks on a 3D printer and achieve an overall energy reduction of 25%.

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Automated OS-level Device Runtime Power Management

Cited by 21 publications

References 21 publications

Declarative Power Sequencing

Declarative Power Sequencing

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