Automated performance‐based design technique for an efficient LTE PDSCH implementation using SDSoC tool

Abstract

System on a chip (SoC) creates massive design challenges for SoC-based designers. The design challenges start from functional, architectural verification complexity and finally meeting performance constraints. In addition, heterogeneity of components and tools introduces long design cycles. The Software-Defined System-on-Chip (SDSoC) developed by Xilinx is used to create custom SoC on a heterogeneous FPGA-CPU platform. The SDSoC tool provides fast, flexible, and short design cycle to develop heterogeneous FPGA-CPU platform. The objective of this paper is to introduce a new automated design technique to build a SoC on a heterogeneous FPGA-CPU platform that meets design requirements using SDSoC tool. In this paper, the typical SDSoC design flow is introduced. In addition, a new automated SDSoC design technique is developed to design SoC on a heterogeneous FPGA-CPU platform on the basis of performance metrics such as area, power, and latency. Design of physical downlink shared channel (PDSCH) in long-term evolution (LTE) is presented as a case study. This paper provides the implementation of the transmitter and the receiver of the PDSCH in LTE using SDSoC tool and selects a platform that meets performance metrics constraints.After refining all C/C++ functions, the SDSoC design flow is executed. 7 The SDSoC design flow is shown in Figure 2. First, all C/C++ functions are compiled, Next, the implementation of the C/C++ functions is partitioned into software implementation functions or hardware-accelerated functions depending on the designer selection.The Vivado tool (Xilinx Inc) and Software Development Kit (SDK) tool are the elements of hardware and software system design, respectively. The Vivado tool includes an HLS tool used for creating the hardware system components by transforming the C/C++ code to an RTL implementation. The SDK tool is a software design suite that includes driver support, C/C++ compiler library, and tools for debugging and profiling. Finally, for integration, the necessary communication blocks between hardware and software are generated automatically by the SDSoC tool, and SoC platform is created by SDSoC tool.The SDSoC tool generates the embedded FPGA SoC platform as shown in Figure 3. This platform allows executing parts of the C/C++ code on the ARM processor as software functions and the other parts of the C/C++ codes on the FPGA as hardware-accelerated functions. The embedded FPGA platform consists of three parts: First, the processing system includes dual-core ARM cortex-A9 processor hardcore processor. Second, interfacing logic includes ACP port interconnect and data movers. Third, hardware logic includes HLS generated block. | Proposed automated performance-based design techniqueThis section illustrates in detail the proposed automated performance-based design technique using SDSoC tool. The objective of this technique is to determine platforms that achieve performance metrics and to select the platform that achieves the best performance. Figure 4 shows the proposed automated performanc...

Design and FPGA-Based Hardware Implementation of NB-IoT Physical Uplink Shared Channel Transmitter and Physical Downlink Shared Channel Receiver

“…The flip-flops that correspond by location to the ones in the CRC polynomial are connected to XORs to be XOR-ed with ones. In the meantime, multiplexers are placed to decide whether the register content or the XOR output will be passed to the next block [10,11].…”

“…Both convolutional encoders comprise three shift registers XOR-ed with the polynomials in (3) and ( 4), and one internal interleaver to change the order of the input bits before entering the second convolutional encoder. In addition, the coding rate of the turbo encoder is 1/3, and therefore, it has three outputs with one output sequence of a systematic channel code that is always identical to the input sequence [11,12].…”

“…, c (K−1) , which are the input to the second 8-state constituent encoder. The relationship between them is as follows [10,11]:…”

“…The main functionality of the rate matching block is to match the number of bits in the transport block to the number of bits that can be transmitted in a given allocation [11]. In addition, it controls the turbo encoder's rate, which gives a 1/3 rate, as the rate can be adjusted according to the downlink control information (DCI) and the channel quality information.…”

“…The block's operation starts with the write state. As the input streams are received serially and then turned into parallel to be stored in the 2D array, a 32-bit serial-to-parallel converter is used to write data row by row [10,11]. Afterward, the read state starts from the ninth column in the first sub-block interleaver or from the nineteenth column in the second sub-block interleaver if the redundancy version value (rv idx ) equals 0 or 2, respectively.…”