Automated source-level error localization in hardware designs

Peischl, Bernhard; Wotawa, Franz

doi:10.1109/mdt.2006.5

Cited by 49 publications

(13 citation statements)

References 11 publications

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“…Future work aims at integrating the EPP model in our Bayesian SFL approach [2], [7], studying the extent of the improvements, as well as comparing our SFL approach to related hardware diagnosis approaches [6], [12], [14]. …”

Section: Discussionmentioning

confidence: 99%

Probabilistic Error Propagation Modeling in Logic Circuits

Gupta

Gemund

Abreu

2011

2011 IEEE Fourth International Conference on Software Testing, Verification and Validation Workshops

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Recent study has shown that accurate knowledge of the false negative rate (FNR) of tests can significantly improve the diagnostic accuracy of spectrum-based fault localization. To understand the principles behind FNR modeling in this paper we study three error propagation probability (EPP) modeling approaches applied to a number of logic circuits from the 74XXX/ISCAS-85 benchmark suite. Monte Carlo simulations for random injected faults show that a deterministic approach that models gate behavior provides high accuracy (O(1%)), while probabilistic approaches that abstract from gate modeling generate higher prediction errors (O(10%)), which increase with the number of injected faults.

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Section: Discussionmentioning

confidence: 99%

Probabilistic Error Propagation Modeling in Logic Circuits

Gupta

Gemund

Abreu

2011

2011 IEEE Fourth International Conference on Software Testing, Verification and Validation Workshops

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“…For example, in Figure 2, the entries in the column C(i) correspond to the suspiciousness score values for all the code items (conditional probabilities), given the sub-tests t 1 , t 5 and t 6 have failed. In the process of fault diagnosis, the ranking of the code items as being the faulty candidate will proceed according to the values C(i) [12].…”

Section: Figure 2 Diagnostic Table For Debugging a Designmentioning

confidence: 99%

“…The majority of the works on automated error localization are in the software development domain [2]- [5]. The error localization approaches for hardware designs are mostly based on formal techniques, such as model-checkers [6] or SAT-solvers [7]- [8], and thus cannot be applied efficiently to large designs. In our previous work [12] we have proposed an approach to automatic localization of design errors based on combining statistical analysis of dynamically covered VHDL code items and static slicing.…”

Section: Introductionmentioning

confidence: 99%

Assessment of diagnostic test for automated bug localization

Tihhomirov

Tsepurov

Jenihhin

et al. 2013

2013 14th Latin American Test Workshop - LATW

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Statistical simulation based design error debug approaches strongly rely on quality of the diagnostic test. At the same time there exists no dedicated technique to perform its quality assessment and engineers are forced to rely on subjective figures such as verification test quality metrics or just the size of the diagnostic test. This paper has proposed two new approaches for assessing diagnostic capability of diagnostic tests for automated bug localization. The first approach relies on probabilistic simulation of diagnostic experiments. The second assessment method is based on calculating Hamming distances of the individual sub-tests in the diagnostic test set. The methods are computationally cheap and they provide for a measure of confidence in the localization results and allow estimating impact of the diagnostic test enhancement. The approach is implemented as a part of an open-source hardware design and debugging framework zamiaCAD. Experimental results with an industrial processor design and a set of documented bugs demonstrate feasibility and effectiveness of the proposed approach.

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“…Console et al [4] show the applicability of MBD to fault localization in logic programs. Much work has been done in applying MBD to hardware designs on the source code level [9,25,20]. The theory has also been successfully applied to debugging programs written in a subset of Java [19,18].…”

Section: Related Workmentioning

confidence: 99%

Automated Fault Localization for C Programs

Griesmayer

Staber

Bloem

2007

Electronic Notes in Theoretical Computer Science

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If a program does not fulfill a given specification, a model checker delivers a counterexample, a run which demonstrates the wrong behavior. Even with a counterexample, locating the actual fault in the source code is often a difficult task for the verification engineer. We present an automatic approach for fault localization in C programs. The method is based on model checking and reports only components that can be changed such that the difference between actual and intended behavior of the example is removed. To identify these components, we use the bounded model checker CBMC on an instrumented version of the program. We present experimental data that supports the applicability of our approach.

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Automated source-level error localization in hardware designs

Cited by 49 publications

References 11 publications

Probabilistic Error Propagation Modeling in Logic Circuits

Probabilistic Error Propagation Modeling in Logic Circuits

Assessment of diagnostic test for automated bug localization

Automated Fault Localization for C Programs

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