Automated Synthesis of Multi-Port Memories and Control

Abstract

High performance systems often employ multiported memories to enhance the throughput and flexibility of the memory. Existing SRAM compilers offer limited control over the SRAM design and port configurations while SRAMs are commonly dual-ported. Experimental designs could benefit from design exploration of multi-port configurations. We propose an open-source, multi-port solution that extends the OpenRAM memory compiler. A parameterized bitcell is presented which can support any combination of read, write, and read-write ports. The bitcell layout is generated for these port combinations, and the SRAM layout can support any combination of two ports. In addition, support for multi-port characterization and functional testing ensures correctness and incorporation into design methodologies.

Macro Memory Cell Generator for SKY130 PDK

“…In the study presented by [13], there is a notable extension of the capabilities originally introduced in OpenRAM as delineated in [12]. This extension features a multi-port solution, enabling the memory compiler within OpenRAM to utilize multi-ported memories.…”

“…As technological applications evolve, the optimization and performance of memory systems, especially those with multi-port configurations, ascend in importance. [13].…”

“…Commercial tools often entail significant costs, potentially placing financial burdens on users, especially smaller organizations or individuals. Furthermore, commercial licenses may come with restrictive terms and limited flexibility, limiting accessibility and adaptability for a broader user base, conversely, open-source tools [9]- [13], in contrast, tend to be more cost-effective, fostering inclusivity and communitydriven development. They often provide greater transparency, enabling users to understand and modify the underlying code, thus encouraging collaboration and innovation within the open-source community.…”

Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach

“…Embedded memories with multiple read/write (R/W) ports are very appealing for modern SoCs [1], [2], [16], [17]. Various blocks that are usually integrated in these systems, such as media and graphics processing units (GPUs) as well as computational cores, require multi-port memories to support instruction-level parallelism with the goal of increasing processing speed while avoiding data serialization and reducing wait states during pipelining [2], [3], [18], [19]. As an example, dual-port memories are widely used for video processing units, since two read and write access operations can be performed within the same clock cycle [20]- [24].…”

“…These memories are often provided with various design targets, such as highdensity, high-speed and low-leakage, but at their basis, they are optimized for size, and are therefore based on foundrysupplied "pushed rule" bitcells, which are very constrained in their usage envelope. For robust operation in advanced process nodes and to meet the high memory throughput re-quirements, the 6T-SRAM macros require dedicated, customdesigned peripherals [2]- [6]. Since these macros are designed for general use, they often do not support special design requirements, such as low-voltage operation, nonstandard array or periphery sizes, multi-ported functionality, etc.…”